參數(shù)資料
型號： ADUC7126BSTZ126-RL
廠商： Analog Devices Inc
文件頁數(shù)： 95/108頁
文件大?。?/td> 0K
描述： IC MCU 16/32B 126KB FLASH 80LQFP
標準包裝： 1,000
系列： MicroConverter® ADuC7xxx
核心處理器： ARM7
芯體尺寸： 16/32-位
速度： 41.78MHz
連通性： EBI/EMI，I²C，SPI，UART/USART
外圍設備： POR，PWM，WDT
輸入/輸出數(shù)： 40
程序存儲器容量： 126KB（63K x 16）
程序存儲器類型： 閃存
RAM 容量： 32K x 8
電壓 - 電源 (Vcc/Vdd)： 2.7 V ~ 3.6 V
數(shù)據(jù)轉(zhuǎn)換器： A/D 12x12b，D/A 4x12b
振蕩器型： 內(nèi)部
工作溫度： -40°C ~ 125°C
封裝/外殼： 80-LQFP
包裝： 帶卷 (TR)
Data Sheet
ADuC7124/ADuC7126
Rev. C | Page 87 of 108
IRQVEC Register
The IRQ interrupt vector register, IRQVEC points to a memory
address containing a pointer to the interrupt service routine of
the currently active IRQ. This register should only be read when
an IRQ occurs and IRQ interrupt nesting has been enabled by
setting Bit 0 of the IRQCONN register.
Name:
IRQVEC
Address:
0xFFFF001C
Default Value:
0x00000000
Access:
Read only
Table 129. IRQVEC MMR Bit Descriptions
Bit
Type
Initial
Value
Description
[31:23]
R
0
Always read as 0.
[22:7]
R/W
0
IRQBASE register value.
[6:2]
R
0
Highest priority source. This is a
value between 0 and 27 represent-
ing the possible interrupt sources.
For example, if the highest currently
active IRQ is Timer 2, then these bits
are [00100].
[1:0]
Reser
ved
0
Reserved bits.
Priority Registers
The IRQ interrupt vector register, IRQVEC points to a memory
address containing a pointer to the interrupt service routine of
the currently active IRQ. This register should only be read when
an IRQ occurs and IRQ interrupt nesting has been enabled by
setting Bit 0 of the IRQCONN register.
IRQP0 Register
Name:
IRQP0
Address:
0xFFFF0020
Default Value:
0x00000000
Access:
Read/write
Table 130. IRQP0 MMR Bit Descriptions
Bit
Name
Description
31
Reserved.
[30:28]
Flash1PI
A priority level of 0 to 7 can be set for the
Flash Block 1 controller interrupt source.
27
Reserved.
[26:24]
Flash0PI
A priority level of 0 to 7 can be set for the
Flash Block 0 controller interrupt source.
23
Reserved.
[22:20]
T3PI
A priority level of 0 to 7 can be set for
Timer 3.
19
Reserved.
Bit
Name
Description
[18:16]
T2PI
A priority level of 0 to 7 can be set for
Timer2.
15
Reserved.
[14:12]
T1PI
A priority level of 0 to 7 can be set for
Timer1.
11
Reserved.
[10:8]
T0PI
A priority level of 0 to 7 can be set for
Timer0.
7
Reserved.
[6:4]
SWINTP
A priority level of 0 to 7 can be set for the
software interrupt source.
[3:0]
Interrupt 0 cannot be prioritized.
IRQP1 Register
Name:
IRQP1
Address:
0xFFFF0024
Default Value:
0x00000000
Access:
Read/write
Table 131. IRQP1 MMR Bit Descriptions
Bit
Name
Description
31
Reserved.
[30:28]
I2C1SPI
A priority level of 0 to 7 can be set for the
I2C1 slave.
27
Reserved.
[26:24]
I2C1MPI
A priority level of 0 to 7 can be set for the
I2C1 master.
23
Reserved.
[22:20]
I2C0SPI
A priority level of 0 to 7 can be set for the
I2C0 slave.
19
Reserved.
[18:16]
I2C0MPI
A priority level of 0 to 7 can be set for the
I2C 0 master.
15
Reserved.
[14:12]
PLLPI
A priority level of 0 to 7 can be set for the
PLL lock interrupt.
11
Reserved.
[10:8]
UART1PI
A priority level of 0 to 7 can be set for
UART1.
7
Reserved.
[6:4]
UART0PI
A priority level of 0 to 7 can be set for
UART0.
5
Reserved.
[2:0]
ADCPI
A priority level of 0 to 7 can be set for the
ADC interrupt source.
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