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| 型號： | ADUC7122BBCZ |
| 廠商： | Analog Devices Inc |
| 文件頁數(shù)： | 15/96頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC ARM7TDMI MCU 126KB 108CSPBGA |
| 特色產(chǎn)品： | ADuC7122 Precision Analog Microcontroller |
| 標準包裝： | 1 |
| 系列： | MicroConverter® ADuC7xxx |
| 核心處理器： | ARM7 |
| 芯體尺寸： | 16/32-位 |
| 速度： | 41.78MHz |
| 連通性： | I²C，SPI，UART/USART |
| 外圍設(shè)備： | POR，PWM，WDT |
| 輸入/輸出數(shù)： | 32 |
| 程序存儲器容量： | 126KB（63K x 16） |
| 程序存儲器類型： | 閃存 |
| RAM 容量： | 8K x 8 |
| 電壓 - 電源 (Vcc/Vdd)： | 3 V ~ 3.6 V |
| 數(shù)據(jù)轉(zhuǎn)換器： | A/D 13x12b，D/A 12x12b |
| 振蕩器型： | 內(nèi)部 |
| 工作溫度： | -10°C ~ 95°C |
| 封裝/外殼： | 108-LFBGA，CSPBGA |
| 包裝： | 托盤 |
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ADuC7122
Rev. 0 | Page 22 of 96
MEMORY ORGANIZATION
The ADuC7122 incorporates three separate blocks of memory:
8 kB of SRAM and two 64 kB of on-chip Flash/EE memory.
There are 126 kB of on-chip Flash/EE memory available to the
user, and the remaining 2 kB are reserved for the factory-
configured boot page. These two blocks are mapped as shown
Note that by default, after a reset, the Flash/EE memory is
mirrored at Address 0x00000000. It is possible to remap the
SRAM at Address 0x00000000 by clearing Bit 0 of the REMAP
MMR. This remap function is described in more detail in the
Flash/EE Memory section.
RESERVED
0x00080000
FLASH/EE
RESERVED
0x00041FFF
0x00040000
SRAM
0xFFFF0000
0xFFFFFFFF
MMRs
0x0001FFFF
0x00000000
0x0009F800
RESERVED
REMAPPABLE MEMORY SPACE
(FLASH/EE OR SRAM)
08
75
5-
00
9
Figure 9. Physical Memory Map
Memory Access
The ARM7 core sees memory as a linear array of 232 byte loca-
tions, where the different blocks of memory are mapped as
outlined in Figure 9.
The ADuC7122 memory organization is configured in little
endian format: the least significant byte is located in the lowest
byte address and the most significant byte in the highest byte
address.
BIT 31
BYTE 2
A
6
2
.
BYTE 3
B
7
3
.
BYTE 1
9
5
1
.
BYTE 0
8
4
0
.
BIT 0
32 BITS
0xFFFFFFFF
0x00000004
0x00000000
08
75
5-
01
0
Figure 10. Little Endian Format
FLASH/EE MEMORY
The 128 kB of Flash/EE are organized as two banks of 32k ×
16 bits. In the upper memory block, 31k × 16 bits are user
space, and 1k × 16 bits are reserved for the factory-configured
boot page. The page size of this Flash/EE memory is 512 bytes.
The lower 64 kB memory block is organized in a similar
manner. It is arranged in 32k × 16 bits. All of this is available as
user space.
The 126 kB of Flash/EE are available to the user as code and
nonvolatile data memory. There is no distinction between data
and program because ARM code shares the same space. The real
width of the Flash/EE memory is 16 bits, meaning that in ARM
mode (32-bit instruction), two accesses to the Flash/EE are
necessary for each instruction fetch. Therefore, it is
recommended that Thumb mode be used when executing from
Flash/EE memory for optimum access speed. The maximum
access speed for the Flash/EE memory is 41.78 MHz in Thumb
mode and 20.89 MHz in full ARM mode (see the Execution
Time from SRAM and FLASH/EE section).
SRAM
The 8 kB of SRAM are available to the user, organized as 2k ×
32 bits, that is, 2k words. ARM code can run directly from SRAM
at 41.78 MHz, given that the SRAM array is configured as a
32-bit wide memory array (see the Execution Time from SRAM
and FLASH/EE section).
MEMORY MAPPED REGISTERS
The memory mapped register (MMR) space is mapped into the
upper two pages of the memory array and accessed by indirect
addressing through the ARM7 banked registers.
The MMR space provides an interface between the CPU and all
on-chip peripherals. All registers except the core registers reside
in the MMR area. All shaded locations shown in Figure 11 are
unoccupied or reserved locations and should not be accessed by
user software. Table 10 to Table 26 show a full MMR memory map.
The access time reading or writing a MMR depends on the
advanced microcontroller bus architecture (AMBA) bus used to
access the peripheral. The processor has two AMBA buses:
advanced high performance bus (AHB) used for system
modules and advanced peripheral bus (APB) used for lower
performance peripheral. Access to the AHB is one cycle, and
access to the APB is two cycles. All peripherals on the
ADuC7122 are on the APB except the Flash/EE memory and
the GPIOs.
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