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參數(shù)資料
| 型號(hào)： | ADUC7022BCP |
| 廠商： | ANALOG DEVICES INC |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 32-BIT, FLASH, 45.5 MHz, RISC MICROCONTROLLER, QCC40 |
| 封裝： | 6 X 6 MM, MO-220VJJD-2, LFCSP-40 |
| 文件頁(yè)數(shù)： | 4/16頁(yè) |
| 文件大?。?/td> | 199K |
| 代理商： | ADUC7022BCP |
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ADuC7020/ADuC7021/ADuC7022
Preliminary Technical Data
Rev. PrC | Page 12 of 16
Figure 4: little endian format
Flash/EE Memory
The total 64kBytes of Flash/EE are organised as 32k X 16 bits.
31k X 16 bits are user space and 1k X 16 bits is reserved for boot
loader. The page size of this Flash/EE memory is 256Bytes.
62kBytes of Flash/EE are available to the user as code and non-
volatile data memory. There is no distinction between data and
program as ARM code shares the same space. The real width of
the Flash/EE memory is 16 bits, which means that in ARM
mode (32-bit instruction), two accesses to the Flash/EE are
necessary
for
each
instruction
fetch.
It
is
therefore
recommended to use Thumb mode when executing from
Flash/EE memory for optimum access speed. The maximum
access speed for the Flash/EE memory is 45MHz in Thumb
mode and 22.5MHz in full ARM mode. More details on
Flash/EE access time are outlined later in ‘Execution from
SRAM and Flash/EE’ section of this datasheet.
SRAM
8kBytes of SRAM are available to the user, organized as 2k X 32
bits, i.e. 2kWords. ARM code can run directly from SRAM at
45MHz , given that the SRAM array is configured as a 32-bit
wide memory array. More details on SRAM access time are
outlined later in ‘Execution from SRAM and Flash/EE’ section
of this datasheet.
Memory Mapped Registers
The Memory Mapped Register (MMR) space is mapped into
the upper 2 pages of the Flash/EE space and accessed by
indirect addressing through the ARM7 banked registers.
The MMR space provides an interface between the CPU and all
on-chip peripherals. All registers except the core registers
reside in the MMR area. All shaded locations shown in Figure 6
are unoccupied or reserved locations and should not be
accessed by user software. Table 4 shows a full MMR memory
map. The ‘Access’ column corresponds to the access time
reading or writing a MMR. Table 4 shows a full MMR memory
map.
Interrupt
Controller
Remap &
System Control
I2C0
UART
DAC
ADC
PLA
Bandgap
Reference
Power Supply
Monitor
GPIO
Timer 0
PLL &
Oscillator Control
Watchdog
Timer
Flash Control
Interface
General Purpose
Timer
Wake Up
Timer
0xFFFF0000
0xFFFF0110
0xFFFF0320
0xFFFF0310
0xFFFF0300
0xFFFF0238
0xFFFF0220
0xFFFF0600
0xFFFFF400
0xFFFF0B54
0xFFFF0B00
0xFFFF0A14
0xFFFF0A00
0xFFFF0848
0xFFFF0800
0xFFFF0730
0xFFFF0700
0xFFFF0620
0xFFFF0500
0xFFFF0538
0xFFFF0490
0xFFFF048C
0xFFFF0334
0xFFFF0448
0xFFFF0440
0xFFFF0420
0xFFFF0404
0xFFFF0340
0xFFFF0350
0xFFFF0360
0xFFFF0370
0xFFFFF46C
0xFFFFFFFF
0xFFFFF800
0xFFFFF820
I2C1
0xFFFF0948
0xFFFF0900
SPI
Figure 5: Memory Mapped
32 bits
Byte0
Byte1
Byte2
Byte3
0x00000000h
0x00000004h
bit0
bit31
0
1
2
3
4
5
6
7
8
9
A
B
..
.
...
..
.
0xFFFFFFFFh
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