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參數(shù)資料
| 型號(hào)： | ADUC7022BCP |
| 廠商： | ANALOG DEVICES INC |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 32-BIT, FLASH, 45.5 MHz, RISC MICROCONTROLLER, QCC40 |
| 封裝： | 6 X 6 MM, MO-220VJJD-2, LFCSP-40 |
| 文件頁數(shù)： | 2/16頁 |
| 文件大小： | 199K |
| 代理商： | ADUC7022BCP |
ADuC7020/ADuC7021/ADuC7022
Preliminary Technical Data
Rev. PrC | Page 10 of 16
GENERAL DESCRIPTION
The ADuC7020/21/22 are fully integrated, 1MSPS, 12-bit data
acquisition systems incorporating a high performance multi-
channel ADC, a 16/32-bit MCU and Flash/EE Memory on a
single chip.
The ADC consists of 5/8/10 single-ended inputs. An additional
2/4 inputs are available on the ADuC7021/20 but are
multiplexed with the 2/4 DAC output pins. The ADC can
operate in single-ended or differential input modes with a fully
flexible front end. The ADC input voltage is 0 to VREF. Low drift
bandgap reference, temperature sensor and voltage comparator
complete the ADC peripheral set.
The part also integrates 2/4 buffered voltage output DACs on-
chip. The DAC output range is 0 to AVDD max.
The device operates from the on-chip oscillator and PLL
generating an internal high-frequency clock of 45 MHz. This
clock is routed through a programmable clock divider from
which the MCU core clock operating frequency is generated.
The microcontroller core is an ARM7TDMI, 16/32-bit RISC
machine, offering up to 45 MIPS peak performance. 62k Bytes
of non-volatile Flash/EE are provided on-chip as well as 8k
Bytes of SRAM. Both the Flash/EE and SRAM memory arrays
are mapped into a single linear array.
On-chip factory firmware supports in-circuit serial download
via the UART and JTAG serial interface ports while non-
intrusive emulation is also supported via the JTAG interface.
These features are incorporated into a low cost QuickStart
system supporting this MicroConverter family.
The parts operate from 2.7V to 3.6V and are specified over an
industrial temperature range of -40°C to 85°C. When operating
@45MHz
the
power
dissipation
is
300mW.
The
ADuC7020/21/22 are available in a 40-lead LFCSP package.
OVERVIEW OF THE ARM7TDMI CORE
The ARM7 core is a 32-bit Reduced Instruction Set Computer
(RISC). It uses a single 32-bit bus for instruction and data. The
length of the data can be 8, 16 or 32 bits and the length of the
instruction word is 32 bits.
The ARM7TDMI is an ARM7 core with 4 additional features:
-
T support for the Thumb (16 bit) instruction set.
-
D support for debug
-
M support for long multiplies
-
I include the EmbeddedICE module to support embedded
system debugging.
Thumb mode (T)
An ARM instruction is 32-bits long. The ARM7TDMI
processor supports a second instruction set that has been
compressed into 16-bits, the Thumb instruction set. Faster
execution from 16-bit memory and greater code density can
usually be achieved by using the Thumb instruction set instead
of the ARM instruction set, which makes the ARM7TDMI core
particularly suitable for embedded applications.
However the Thumb mode has two limitations:
-
Thumb code usually uses more instructions for the same job,
so ARM code is usually best for maximising the performance
of the time-critical code.
-
The Thumb instruction set does not include some
instructions that are needed for exception handling, so ARM
code needs to be used for exception handling.
See ARM7TDMI User Guide for details on the core
architecture, the programming model and both the ARM and
ARM Thumb instruction sets.
Long multiple (M)
The
ARM7TDMI
instruction
set
includes
four
extra
instructions which perform 32-bit by 32-bit multiplication with
64-bit result and 32-bit by 32-bit multiplication-accumulation
(MAC) with 64-bit result.
EmbeddedICE (I)
EmbeddedICE provides integrated on-chip support for the core.
The EmbeddedICE module contains the breakpoint and
watchpoint registers which allow code to be halted for
debugging purposes. These registers are controlled through the
JTAG test port.
When a breakpoint or watchpoint is encountered, the processor
halts and enters debug state. Once in a debug state, the
processor registers may be inspected as well as the Flash/EE, the
SRAM and the Memory Mapped Registers.
Exceptions
ARM supports five types of exceptions, and a privileged
processing mode for each type. The five type of exceptions are:
-
Normal interrupt or IRQ. It is provided to service general-
purpose interrupt handling of internal and external events
-
Fast interrupt or FIQ. It is provided to service data transfer or
communication channel with low latency. FIQ has priority
over IRQ
-
Memory abort
-
Attempted execution of an undefined instruction
-
Software interrupt (SWI) instruction which can be used to
make a call to an operating system.
Typically the programmer will define interrupts as IRQ but for
higher priority interrupt, i.e. faster response time, the
programmer can define interrupt as FIQ.
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