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參數(shù)資料
| 型號： | ADUC7022BCP |
| 廠商： | ANALOG DEVICES INC |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 32-BIT, FLASH, 45.5 MHz, RISC MICROCONTROLLER, QCC40 |
| 封裝： | 6 X 6 MM, MO-220VJJD-2, LFCSP-40 |
| 文件頁數(shù)： | 3/16頁 |
| 文件大?。?/td> | 199K |
| 代理商： | ADUC7022BCP |
Preliminary Technical Data
ADuC7020/ADuC7021/ADuC7022
Rev. PrC | Page 11 of 16
ARM Registers
ARM7TDMI has a total of 37 registers, of which 31 are general
purpose registers and six are status registers. Each operating
mode has dedicated banked registers.
When writing user-level programs, 15 general purpose 32-bit
registers (r0 to r14), the program counter (r15) and the current
program status register (CPSR) are usable. The remaining
registers are used only for system-level programming and for
exception handling.
When an exception occurs, some of the standard register are
replaced with registers specific to the exception mode. All
exception modes have replacement banked registers for the
stack pointer (r13) and the link register (r14) as represented in
Figure22. The fast interrupt mode has more registers (8 to 12)
for fast interrupt processing, so that the interrupt processing
can begin without the need to save or restore these registers and
thus save critical time in the interrupt handling process.
Figure22: register organisation
Interrupt latency
The worst case latency for an FIQ, assuming that it is enabled,
consists of the longest time the request can take to pass through
the synchronizer, plus the time for the longest instruction to
complete (the longest instruction is an LDM) which loads all
the registers including the PC, plus the time for the data abort
entry, plus the time for FIQ entry. At the end of this time, the
ARM7TDMI will be executing the instruction at 0x1C (FIQ
interrupt vector address). The maximum total time is 44
processor cycles, which is just over 975 nanoseconds in a system
using a continuous 45 MHz processor clock.
The maximum IRQ latency calculation is similar, but must
allow for the fact that FIQ has higher priority and could delay
entry into the IRQ handling routine for an arbitrary length of
time.
The minimum latency for FIQ or IRQ interrupts is four cycles
in total which consists of the shortest time the request can take
through the synchronizer plus the time to enter the exception
mode.
Note that the ARM7TDMI will always be run in ARM (32-bit)
mode when in privileged modes, i.e. when executing interrupt
service routines.
MEMORY ORGANISATION
The ADuC7020/21/22 incorporate two separate blocks of
memory, 8kByte of SRAM and 64kByte of On-Chip Flash/EE
memory. 62kByte of On-Chip Flash/EE memory are available to
the user, and the remaining 2kBytes are reserved for the factory
configured boot page. These two blocks are mapped as shown
Figure 3.
Note that by default, after a reset, the Flash/EE memory is
mirrored at address 0x00000000. It is possible to remap the
SRAM at address 0x00000000 by clearing bit 0 of the REMAP
MMR. This remap function is described in more details in the
Flash/EE memory chapter.
Re-mappable Memory Space
(Flash/EE or SRAM)
Reserved
00080000h
Flash/EE
Reserved
00011FFFh
00010000h
SRAM
FFFF0000h
FFFFFFFFh
MMRs
0000FFFFh
00000000h
0008FFFFh
Figure 3: Physical memory map
Memory Access
The ARM7 core sees memory as a linear array of 232 byte
location where the different blocks of memory are mapped as
outlined in Figure 3 above.
The ADuC7020/21/22 memory organisation is configured in
little endian format: the least significant byte is located in the
lowest byte address and the most significant byte in the highest
byte address.
user mode
fiq
mode
svc
mode
abord
mode
irq
mode
undefined
mode
r0
r1
r2
r3
r4
r5
r6
r7
r8
r9
r10
r11
r12
r13
r14
r15 (PC)
r8_fiq
r9_fiq
r10_fiq
r11_fiq
r12_fiq
r13_fiq
r14_fiq
r13_svc
r14_svc
r13_abt
r14_abt
r13_irq
r14_irq
r13_und
r14_und
usable in user mode
system modes only
CPSR
SPSR_fiq
SPSR_svc
SPSR_und
SPSR_abt
SPSR_irq
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