參數(shù)資料
型號： ADSP-BF592KCPZ
廠商： Analog Devices Inc
文件頁數(shù)： 28/44頁
文件大?。?/td> 0K
描述： IC DSP CTRLR 64LFCSP
視頻文件： Blackfin? BF592 Introduction
特色產(chǎn)品： Blackfin Embedded Processor
標(biāo)準(zhǔn)包裝： 1
系列： Blackfin®
類型： 定點
接口： I²C，I²S，IrDA，PPI，SPI，SPORT，UART
時鐘速率： 400MHz
非易失內(nèi)存： ROM（64 kB）
芯片上RAM： 64kB
電壓 - 輸入/輸出： 1.8V，2.5V，3.3V
電壓 - 核心： 1.29V
工作溫度： 0°C ~ 70°C
安裝類型： 表面貼裝
封裝/外殼： 64-VFQFN 裸露焊盤，CSP
供應(yīng)商設(shè)備封裝： 64-LFCSP-VQ（9x9）
包裝： 托盤
Rev. B
|
Page 34 of 44
|
July 2013
Timer Cycle Timing
Table 29 and Figure 22 describe timer expired operations. The
input signal is asynchronous in “width capture mode” and
“external clock mode” and has an absolute maximum input fre-
quency of (fSCLK/2) MHz.
Timer Clock Timing
Table 30 and Figure 23 describe timer clock timing.
Table 29. Timer Cycle Timing
Parameter
VDDEXT
1.8V Nominal
VDDEXT
2.5 V/3.3V Nominal
Min
Max
Min
Max
Unit
Timing Requirements
tWL
Timer Pulse Width Input Low
(Measured In SCLK Cycles)1
1 × tSCLK
ns
tWH
Timer Pulse Width Input High
(Measured In SCLK Cycles)1
1 × tSCLK
ns
tTIS
Timer Input Setup Time Before CLKOUT Low2
10
8
ns
tTIH
Timer Input Hold Time After CLKOUT Low2
–2
ns
Switching Characteristics
tHTO
Timer Pulse Width Output
(Measured In SCLK Cycles)
1 × tSCLK – 2
(2
32 – 1) × t
SCLK
tSCLK – 1.5
(2
32 – 1) × t
SCLK
ns
tTOD
Timer Output Update Delay After CLKOUT High
6
ns
1 The minimum pulse widths apply for TMRx signals in width capture and external clock modes. They also apply to the PG0 or PPI_CLK signals in PWM output mode.
2 Either a valid setup and hold time or a valid pulse width is sufficient. There is no need to resynchronize programmable flag inputs.
Figure 22. Timer Cycle Timing
CLKOUT
TMRx OUTPUT
TMRx INPUT
tTIS
tTIH
tWH,tWL
tTOD
tHTO
Table 30. Timer Clock Timing
Parameter
VDDEXT = 1.8 V
VDDEXT = 2.5V/3.3 V
Min
Max
Min
Max
Unit
Switching Characteristic
tTODP
Timer Output Update Delay After PPI_CLK High
12.64
ns
Figure 23. Timer Clock Timing
PPI_CLK
TMRx OUTPUT
tTODP
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