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鍨嬭櫉锛� ADSP-BF592KCPZ
寤犲晢锛� Analog Devices Inc
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鐗硅壊鐢�(ch菐n)鍝侊細 Blackfin Embedded Processor
妯�(bi膩o)婧�(zh菙n)鍖呰锛� 1
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椤炲瀷锛� 瀹氶粸
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鑺墖涓奟AM锛� 64kB
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闆诲 - 鏍稿績锛� 1.29V
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瀹夎椤炲瀷锛� 琛ㄩ潰璨艰
灏佽/澶栨锛� 64-VFQFN 瑁搁湶鐒婄洡锛孋SP
渚涙噳(y墨ng)鍟嗚ō(sh猫)鍌欏皝瑁濓細 64-LFCSP-VQ锛�9x9锛�
鍖呰锛� 鎵樼洡
Rev. B
|
Page 30 of 44
|
July 2013
Table 25. Serial Ports鈥擥ated Clock Mode
VDDEXT
1.8V Nominal
VDDEXT
2.5 V/3.3 V Nominal
Parameter
Min
Max
Min
Max
Unit
Timing Requirements
tSDRI
Receive Data Setup Before TSCLKx
11.3
8.7
ns
tHDRI
Receive Hold After TSCLKx
0
ns
Switching Characteristics
tDDTI
Transmit Data Delay After TSCLKx
3
ns
tHDTI
Transmit Data Hold After TSCLKx
鈥�1.8
ns
tDFTSCLKCNV
First TSCLKx edge delay after TFSx/TMR1 Low
0.5 脳 tTSCLK 鈥� 3
ns
tDCNVLTSCLK
TFSx/TMR1 High Delay After Last TSCLKx Edge
tTSCLK 鈥� 3
ns
Figure 18. Serial Ports Gated Clock Mode
TSCLKx
(OUT)
GATED CLOCK MODE DATA RECEIVE
TFS/TMR
(OUT)
DTx
DELAY TIME DATA TRANSMIT
tHDRI
tSDRI
TSCLKx
(OUT)
TSCLKx
(OUT)
tDDTI
tHDTI
DRx
tDFTSCLKCNV
tDCNVLTSCLK
tDFTSCLKCNV
鐩搁棞(gu膩n)PDF璩囨枡
PDF鎻忚堪
TOP224G IC OFFLINE SWIT PWM OCP HV 8SMD
EMA44DRMN CONN EDGECARD 88POS .125 SQ WW
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DRA73-470-R INDUCTOR HI TEMP 47UH 1.02A SMD
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