參數(shù)資料
型號(hào)： ADSP-BF592KCPZ
廠商： Analog Devices Inc
文件頁(yè)數(shù)： 1/44頁(yè)
文件大小： 0K
描述： IC DSP CTRLR 64LFCSP
視頻文件： Blackfin? BF592 Introduction
特色產(chǎn)品： Blackfin Embedded Processor
標(biāo)準(zhǔn)包裝： 1
系列： Blackfin®
類型： 定點(diǎn)
接口： I²C，I²S，IrDA，PPI，SPI，SPORT，UART
時(shí)鐘速率： 400MHz
非易失內(nèi)存： ROM（64 kB）
芯片上RAM： 64kB
電壓 - 輸入/輸出： 1.8V，2.5V，3.3V
電壓 - 核心： 1.29V
工作溫度： 0°C ~ 70°C
安裝類型： 表面貼裝
封裝/外殼： 64-VFQFN 裸露焊盤，CSP
供應(yīng)商設(shè)備封裝： 64-LFCSP-VQ（9x9）
包裝： 托盤
Blackfin and the Blackfin logo are registered trademarks of Analog Devices, Inc.
Blackfin
Embedded Processor
Rev. B
Information furnished by Analog Devices is believed to be accurate and reliable.
However, no responsibility is assumed by Analog Devices for its use, nor for any
infringements of patents or other rights of third parties that may result from its use.
Specifications subject to change without notice. No license is granted by implication
or otherwise under any patent or patent rights of Analog Devices. Trademarks and
registered trademarks are the property of their respective companies.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106 U.S.A.
Tel: 781.329.4700
2013 Analog Devices, Inc. All rights reserved.
FEATURES
Up to 400 MHz high performance Blackfin processor
Two 16-bit MACs, two 40-bit ALUs, four 8-bit video ALUs,
40-bit shifter
RISC-like register and instruction model for ease of
programming and compiler-friendly support
Advanced debug, trace, and performance monitoring
Accepts a wide range of supply voltages for internal and I/O
Off-chip voltage regulator interface
64-lead (9 mm × 9 mm) LFCSP package
MEMORY
68K bytes of core-accessible memory
(See Table 1 on Page 3 for L1 and L3 memory size details)
64K byte L1 instruction ROM
Flexible booting options from internal L1 ROM and SPI mem-
ory or from host devices including SPI, PPI, and UART
Memory management unit providing memory protection
PERIPHERALS
Four 32-bit timers/counters, three with PWM support
2 dual-channel, full-duplex synchronous serial ports (SPORT),
supporting eight stereo I
2S channels
2 serial peripheral interface (SPI) compatible ports
1 UART with IrDA support
Parallel peripheral interface (PPI), supporting ITU-R 656
video data formats
2-wire interface (TWI) controller
9 peripheral DMAs
2 memory-to-memory DMA channels
Event handler with 28 interrupt inputs
32 general-purpose I/Os (GPIOs), with programmable
hysteresis
Debug/JTAG interface
On-chip PLL capable of frequency multiplication
Figure 1. Processor Block Diagram
SPORT0
VOLTAGE REGULATOR INTERFACE
PORT F
JTAG TEST AND EMULATION
PERIPHERAL
ACCESS BUS
WATCHDOG TIMER
PPI
SPI0
SPI1
BOOT
ROM
DMA
ACCESS
BUS
INTERRUPT
CONTROLLER
DMA
CONTROLLER
L1 DATA
SRAM
L1 INSTRUCTION
SRAM
DCB
B
UART
DEB
TIMER2–0
L1 INSTRUCTION
ROM
GPIO
SPORT1
TWI
PORT G
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