參數(shù)資料
型號: ADSP-BF547KBCZ-6A
廠商: ANALOG DEVICES INC
元件分類: 數(shù)字信號處理
英文描述: 600 MHz Blackfin Embedded Processor: ADSP-BF547KBCZ-6A Temp Range: 0°C to +70°C Package: 400-Ball CSP_BGA BC-400-1
中文描述: 16-BIT, 50 MHz, OTHER DSP, PBGA400
封裝: 17 X 17 MM, ROHS COMPLIANT, CSBGA-400
文件頁數(shù): 78/100頁
文件大?。?/td> 3095K
代理商: ADSP-BF547KBCZ-6A
ADSP-BF542/ADSP-BF544/ADSP-BF547/ADSP-BF548/ADSP-BF549
Rev. D
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Page 79 of 100
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May 2011
ATAPI Ultra DMA Data-In Transfer Timing
Table 60 and Figure 53 through Figure 56 describe the ATAPI
ultra DMA data-in data transfer timing. The material in these
figures is adapted from ATAPI-6 (INCITS 361-2002[R2007]
and is used with permission of the American National Stan-
dards Institute (ANSI) on behalf of the Information Technology
Industry Council (“ITIC”). Copies of ATAPI-6 (INCITS 361-
2002[R2007] can be purchased from ANSI.
Table 60. ATAPI Ultra DMA Data-In Transfer Timing
ATAPI Parameter
ATAPI_ULTRA_TIM_x Timing
Register Setting
1
Timing Equation
tDS
Data setup time at host
N/A
TSK3 + tSUDU
tDH
Data hold time at host
N/A
TSK3 + tHDU
tCVS
CRC word valid setup time at host
TDVS
TDVS × tSCLK – (tSK1 + tSK2)
tCVH
CRC word valid hold time at host
TACK
TACK × tSCLK – (tSK1 + tSK2)
tLI
Limited interlock time
N/A
2 × tBD + 2 × tSCLK + tOD
tMLI
Interlock time with minimum
TZAH, TCVS
(TZAH + TCVS) × tSCLK – (4 × tBD + 4 × tSCLK + 2 × tOD)
tAZ
Maximum time allowed for output drivers to
release
N/A
0
tZAH
Minimum delay time required for output
TZAH
2 × tSCLK + TZAH × tSCLK + tSCLK
tENV
2
ATAPI_DMACK to ATAPI_DIOR/DIOW
TENV
(TENV × tSCLK) +/– (tSK1 + tSK2)
tRP
ATAPI_DMACK to ATAPI_DIOR/DIOW
TRP
TRP × tSCLK – (tSK1 + tSK2 + tSK4)
tACK
Setup and hold times for ATAPI_DMACK
TACK
TACK × tSCLK – (tSK1 + tSK2)
1 ATAPI Timing Register Setting should be programmed with a value that guarantees parameter compliance with the ATA ANSI specification for ATA device mode of operation.
2 This timing equation can be used to calculate both the minimum and maximum t
ENV.
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