參數(shù)資料
型號: ADSP-BF547KBCZ-6A
廠商: ANALOG DEVICES INC
元件分類: 數(shù)字信號處理
英文描述: 600 MHz Blackfin Embedded Processor: ADSP-BF547KBCZ-6A Temp Range: 0°C to +70°C Package: 400-Ball CSP_BGA BC-400-1
中文描述: 16-BIT, 50 MHz, OTHER DSP, PBGA400
封裝: 17 X 17 MM, ROHS COMPLIANT, CSBGA-400
文件頁數(shù): 27/100頁
文件大小: 3095K
代理商: ADSP-BF547KBCZ-6A
Rev. D
|
Page 32 of 100
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May 2011
ADSP-BF542/ADSP-BF544/ADSP-BF547/ADSP-BF548/ADSP-BF549
Supplies
VDDINT
P
Internal Power Supply
VDDEXT
12
P
External Power Supply
VDDDDR
P
External DDR Power Supply
VDDUSB
P
External USB Power Supply
VDDRTC
P
RTC Clock Supply
VDDVR
13
P
Internal Voltage Regulator Power Supply (Connect to VDDEXT
when unused.)
GND
G
Ground
VDDMP
P
MXVR PLL Power Supply. (Must be driven to same level as VDDINT. Connect
to VDDINT when unused or when MXVR is not present.)
GNDMP
G
MXVR PLL Ground (Connect to GND when unused or when MXVR is not
present.)
1 I = Input, O = Output, P =Power, G = Ground, C = Crystal, A = Analog.
2 Refer to Table 62 on Page 86 through Table 71 on Page 87 for driver types.
3 To use the SPI memory boot, SPI0SCK should have a pulldown, SPI0MISO should have a pullup, and SPI0SEL1 is used as the CS with a pullup.
4 HWAIT/HWAITA should be pulled high or low to configure polarity. See Booting Modes on Page 18.
5 GPW functionality is available when MXVR is not present or unused.
6 This pin should not be used as GPIO if booting in mode 1.
7 This pin should always be enabled as ND_CE in software and pulled high with a resistor when using NAND flash.
8 This pin should always be enabled as BR in software and pulled high to enable asynchronous access.
9 This pin must be pulled low through a 10kOhm resistor if self-refresh mode is desired during hibernate state or deep-sleep mode.
10If the USB is used in device mode only, the USB_ID pin should be either pulled high or left unconnected.
11This pin is an output only during initialization of USB OTG session request pulses in peripheral mode. Therefore, host mode or OTG type A mode requires that an external
voltage source of 5 V, at 8 mA or more per the OTG specification, be applied to this pin. Other OTG modes require that this external voltage be disabled.
12To ensure proper operation, the power pins should be driven to their specified level even if the associated peripheral is not used in the application.
13This pin must always be connected. If the internal voltage regulator is not being used, this pin may be connected to V
DDEXT. Otherwise it should be powered according to the
VDDVR specification. For automotive grade models, the internal voltage regulator must not be used and this pin must be tied to VDDEXT.
Table 11. Pin Descriptions
(Continued)
Pin Name
I/O
1 Function (First/Second/Third/Fourth)
Driver
Type
2
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