參數(shù)資料
型號: ADSP-BF535PBB-300
廠商: Analog Devices Inc
文件頁數(shù): 23/44頁
文件大?。?/td> 0K
描述: IC DSP CONTROLLER 16BIT 260BGA
產(chǎn)品培訓模塊: Blackfin® Processor Core Architecture Overview
Blackfin® Device Drivers
Blackfin® Optimizations for Performance and Power Consumption
Blackfin® System Services
標準包裝: 1
系列: Blackfin®
類型: 定點
接口: PCI,SPI,SSP,UART,USB
時鐘速率: 300MHz
非易失內(nèi)存: 外部
芯片上RAM: 308kB
電壓 - 輸入/輸出: 3.30V
電壓 - 核心: 1.50V
工作溫度: -40°C ~ 85°C
安裝類型: 表面貼裝
封裝/外殼: 260-BBGA
供應(yīng)商設(shè)備封裝: 260-PBGA(19x19)
包裝: 托盤
–3–
REV. A
ADSP-BF535
Clock, Programmable Flags, Watchdog Timer, and USB and
PCI buses for glueless peripheral expansion.
ADSP-BF535 Peripherals
The ADSP-BF535 Blackfin processor contains a rich set of
peripherals connected to the core via several high bandwidth
buses, providing flexibility in system configuration as well as
excellent overall system performance. See Functional Block
Diagram on Page 1. The base peripherals include general-
purpose functions such as UARTs, timers with PWM (Pulse
Width Modulation) and pulse measurement capability, general-
purpose flag I/O pins, a real-time clock, and a watchdog timer.
This set of functions satisfies a wide variety of typical system
support needs and is augmented by the system expansion capa-
bilities of the part. In addition to these general-purpose
peripherals, the ADSP-BF535 Blackfin processor contains high
speed serial ports for interfaces to a variety of audio and modem
CODEC functions. It also contains an event handler for flexible
management of interrupts from the on-chip peripherals and
external sources. And it contains power management control
functions to tailor the performance and power characteristics of
the processor and system to many application scenarios.
The on-chip peripherals can be easily augmented in many system
designs with little or no glue logic due to the inclusion of several
interfaces providing expansion on industry-standard buses.
These include a 32-bit, 33 MHz, V2.2 compliant PCI bus, SPI
serial expansion ports, and a device type USB port. These enable
the connection of a large variety of peripheral devices to tailor the
system design to specific applications with a minimum of design
complexity.
All of the peripherals, except for programmable flags, real-time
clock, and timers, are supported by a flexible DMA structure with
individual DMA channels integrated into the peripherals. There
is also a separate memory DMA channel dedicated to data
transfers between the various memory spaces including external
SDRAM and asynchronous memory, internal Level 1 and Level
2 SRAM, and PCI memory spaces. Multiple on-chip 32-bit
buses, running at up to 133 MHz, provide adequate bandwidth
to keep the processor core running along with activity on all of
the on-chip and external peripherals.
Processor Core
As shown in Figure 1, the Blackfin processor core contains two
multiplier/accumulators (MACs), two 40-bit ALUs, four video
ALUs, and a single shifter. The computational units process
8-bit, 16-bit, or 32-bit data from the register file.
Each MAC performs a 16-bit by 16-bit multiply in every cycle,
with an accumulation to a 40-bit result, providing 8 bits of
extended precision.
The ALUs perform a standard set of arithmetic and logical oper-
ations. With two ALUs capable of operating on 16- or 32-bit data,
the flexibility of the computation units covers the signal process-
ing requirements of a varied set of application needs. Each of the
two 32-bit input registers can be regarded as two 16-bit halves,
so each ALU can accomplish very flexible single 16-bit arithmetic
operations. By viewing the registers as pairs of 16-bit operands,
dual 16-bit or single 32-bit operations can be accomplished in a
single cycle. Quad 16-bit operations can be accomplished simply,
by taking advantage of the second ALU. This accelerates the per
cycle throughput.
Figure 1. Processor Core
SP
SEQU ENCE R
AL IGN
DEC ODE
L OOP BUF F ER
DA G0
DAG1
16
8
40
A0
A1
BA RR EL
SHIFTER
DA T A AR ITH MET IC UN IT
CONTROL
UNIT
ADD RESS A RIT HMET IC U NIT
FP
P5
P4
P3
P2
P1
P0
R7
R6
R5
R4
R3
R2
R1
R0
I3
I2
I1
I0
L3
L2
L1
L0
B3
B2
B1
B0
M3
M2
M1
M0
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