參數(shù)資料
型號(hào)： ADSP-BF506KSWZ-3F
廠商： Analog Devices Inc
文件頁(yè)數(shù)： 9/80頁(yè)
文件大小： 0K
描述： IC DSP 12BIT 300MHZ 120LQFP
視頻文件： Blackfin? BF50x Processor Family
標(biāo)準(zhǔn)包裝： 1
系列： Blackfin®
類型： 定點(diǎn)
接口： CAN，EBI/EMI，I²C，IrDA，PPI，SPI，SPORT，UART/USART
時(shí)鐘速率： 300MHz
非易失內(nèi)存： 閃存（16MB）
芯片上RAM： 68kB
電壓 - 輸入/輸出： 3.30V
電壓 - 核心： 1.29V
工作溫度： 0°C ~ 70°C
安裝類型： 表面貼裝
封裝/外殼： 120-LQFP 裸露焊盤
供應(yīng)商設(shè)備封裝： 120-LQFP-EP（14x14）
包裝： 托盤
Rev. A
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Page 17 of 80
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July 2011
ADSP-BF504/ADSP-BF504F/ADSP-BF506F
Boot from serial SPI memory, EEPROM or flash
(BMODE = 0x3)—8-, 16-, 24-, or 32-bit addressable
devices are supported. The processor uses the PF13 GPIO
pin to select a single SPI EEPROM/flash device (connected
to the SPI0 interface) and submits a read command and
successive address bytes (0x00) until a valid 8-, 16-, 24-, or
32-bit addressable device is detected. Pull-up resistors are
required on the SPI0_SEL1 and MISO pins. By default, a
value of 0x85 is written to the SPI_BAUD register.
Boot from SPI host device (BMODE = 0x4)—The proces-
sor operates in SPI slave mode and is configured to receive
the bytes of the LDR file from an SPI host (master) agent.
The HWAIT signal must be interrogated by the host before
every transmitted byte. A pull-up resistor is required on the
SPI0_SS input. A pull-down on the serial clock (SCK) may
improve signal quality and booting robustness.
Boot from PPI host device (BMODE = 0x5)—The proces-
sor operates in PPI slave mode and is configured to receive
the bytes of the LDR file from a PPI host (master) agent.
Boot from UART0 host on Port G (BMODE = 0x7)—
Using an autobaud handshake sequence, a boot-stream for-
matted program is downloaded by the host. The host
selects a bit rate within the UART clocking capabilities.
When performing the autobaud detection, the UART
expects an “@” (0x40) character (eight bits data, one start
bit, one stop bit, no parity bit) on the UA0_RX pin to deter-
mine the bit rate. The UART then replies with an
acknowledgement composed of 4 bytes (0xBF, the value of
UART0_DLL, the value of UART0_DLH, then 0x00). The
host can then download the boot stream. The processor
deasserts the UA0_RTS output to hold off the host;
UA0_CTS functionality is not enabled at boot time.
For each of the boot modes, a 16 byte header is first read from
an external memory device. The header specifies the number of
bytes to be transferred and the memory destination address.
Multiple memory blocks may be loaded by any boot sequence.
Once all blocks are loaded, program execution commences from
the address stored in the EVT1 register.
The boot kernel differentiates between a regular hardware reset
and a wakeup-from-hibernate event to speed up booting in the
later case. Bits 6-4 in the system reset configuration (SYSCR)
register can be used to bypass the pre-boot routine and/or boot
kernel in case of a software reset. They can also be used to simu-
late a wakeup-from-hibernate boot in the software reset case.
The boot process can be further customized by “initialization
code.” This is a piece of code that is loaded and executed prior to
the regular application boot. Typically, this is used to speed up
booting by managing the PLL, clock frequencies, wait states, or
serial bit rates.
The boot ROM also features C-callable functions that can be
called by the user application at run time. This enables second-
stage boot or boot management schemes to be implemented
with ease.
INSTRUCTION SET DESCRIPTION
The Blackfin processor family assembly language instruction set
employs an algebraic syntax designed for ease of coding and
readability. The instructions have been specifically tuned to
provide a flexible, densely encoded instruction set that compiles
to a very small final memory size. The instruction set also
provides fully featured multifunction instructions that allow the
programmer to use many of the processor core resources in a
single instruction. Coupled with many features more often seen
on microcontrollers, this instruction set is very efficient when
compiling C and C++ source code. In addition, the architecture
supports both user (algorithm/application code) and supervisor
(O/S kernel, device drivers, debuggers, ISRs) modes of opera-
tion, allowing multiple levels of access to core processor
resources.
The assembly language, which takes advantage of the proces-
sor’s unique architecture, offers the following advantages:
Seamlessly integrated DSP/MCU features are optimized for
both 8-bit and 16-bit operations.
A multi-issue load/store modified-Harvard architecture,
which supports two 16-bit MAC or four 8-bit ALU + two
load/store + two pointer updates per cycle.
All registers, I/O, and memory are mapped into a unified
4G byte memory space, providing a simplified program-
ming model.
Microcontroller features, such as arbitrary bit and bit-field
manipulation, insertion, and extraction; integer operations
on 8-, 16-, and 32-bit data-types; and separate user and
supervisor stack pointers.
Code density enhancements, which include intermixing of
16-bit and 32-bit instructions (no mode switching, no code
segregation). Frequently used instructions are encoded
in 16 bits.
DEVELOPMENT TOOLS
The processor is supported with a complete set of
CROSSCORE
software and hardware development tools,
including Analog Devices emulators and VisualDSP++
devel-
opment environment. The same emulator hardware that
supports other Blackfin processors also fully emulates the
ADSP-BF50x processors.
EZ-KIT Lite Evaluation Board
For evaluation of ADSP-BF50x processors, use the EZ-KIT Lite
boards soon to be available from Analog Devices. When these
evaluation kits are available, order using part number
ADZS-BF506-EZLITE. The boards come with on-chip
emulation capabilities and is equipped to enable software
development. Multiple daughter cards will be available.
DESIGNING AN EMULATOR-COMPATIBLE
PROCESSOR BOARD (TARGET)
The Analog Devices family of emulators are tools that every sys-
tem developer needs in order to test and debug hardware and
software systems. Analog Devices has supplied an IEEE 1149.1
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