參數(shù)資料
型號: ADSP-21MOD980N
廠商: Analog Devices, Inc.
英文描述: MultiPort Internet Gateway Processor
中文描述: 通寶互聯(lián)網(wǎng)網(wǎng)關(guān)處理器
文件頁數(shù): 33/42頁
文件大?。?/td> 566K
代理商: ADSP-21MOD980N
33
REV. PrB
6/2001
For current information contact Analog Devices at (800) ANALOGD
ADSP-21mod980N
PRELIMINARY TECHNICAL DATA
IDMA Read, Long Read Cycle
Table 15. IDMA Read, Long Read Cycle
Parameter
Description
Min.
Max
Unit
Timing Requirements:
t
IKR
IACK Low before Start of Read
1, 2
0
ns
t
IRK
End of Read after IACK Low
2,
3
2
ns
Switching Characteristics:
t
IKHR
IACK High after Start of Read
1, 2
10
ns
t
IKDS
IAD[15:0 Data Setup before IACK Low
2
0.5t
CK
- 2
ns
t
IKDH
IAD[15:0] Data Hold after End of Read
2, 3
0
ns
t
IKDD
IAD[15:0] Data Disabled after End of Read
2, 3
10
ns
t
IRDE
IAD[15:0] Previous Data Enabled after Start of Read
2
0
ns
t
IRDV
IAD[15:0] Previous Data Valid after Start of Read
2
10
ns
t
IRDH
1
IAD[15:0] Previous Data Hold after Start of Read
(DM/PM1)
2, 4
2t
CK
- 5
ns
t
IRDH
2
IAD[15:0] Previous Data Hold after Start of Read (PM2)
2, 5
t
CK
- 5
ns
1
Start of Read = IS Low and IRD Low.
2
For IDMA, please refer to the
ADSP-2100 Family User
s Manual
.
3
End of Read = IS High or IRD High.
4
DM read or first half of PM read.
5
Second half of PM read.
Figure 25. IDMA Read, Long Read Cycle
t
IRK
t
IKR
PREVIOUS
DATA
READ
DATA
t
IKHR
t
IKDS
t
IRDV
t
IRDH
t
IKDD
t
IRDE
t
IKDH
IAD 15-0
IACK
IS
IRD
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