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參數(shù)資料
| 型號(hào)： | ADSP-21MOD980N-000 |
| 廠商： | ANALOG DEVICES INC |
| 元件分類： | 通信及網(wǎng)絡(luò) |
| 英文描述： | CAP 27PF 100V 10% X7R AXIAL BULK M-MIL-PRF-39014 |
| 中文描述： | SPECIALTY TELECOM CIRCUIT, PBGA352 |
| 封裝： | 35 X 35 MM, PLASTIC, BGA-352 |
| 文件頁數(shù)： | 35/42頁 |
| 文件大?。?/td> | 566K |
| 代理商： | ADSP-21MOD980N-000 |
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35
REV. PrB
6/2001
For current information contact Analog Devices at (800) ANALOGD
ADSP-21mod980N
PRELIMINARY TECHNICAL DATA
IDMA Read - Short Read Cycle in Short Read Only Mode
Table 17. IDMA Read - Short Read Cycle in Short Read Only Mode
1
1
Short Read Only is enabled by setting Bit 14 of the IDMA Overlay Register to 1 (0x3FE7). Short Read Only can be enabled by the processor core writing
to the register or by an external host writing to the register. Disabled by default.
2
Start of Read = IS Low and IRD Low. Previous data remains until end of read.
3
End of Read = IS High or IRD High.
4
For IDMA, please refer to the
ADSP-2100 Family User
’
s Manual
.
Parameter
Description
Min.
Max
Unit
Timing Requirements:
t
IKR
IACK Low before Start of Read
2, 4
0
ns
t
IRP
Duration of Read after IACK Low
3, 4
10
ns
Switching Characteristics:
t
IKHR
IACK High after Start of Read
2, 4
10
ns
t
IKDH
IAD[15:0] Previous Data Hold after End of Read
3, 4
0
ns
t
IKDD
IAD[15:0] Previous Data Disabled after End of Read
3, 4
10
ns
t
IRDE
IAD[15:0] Previous Data Enabled after Start of Read
4
0
ns
t
IRDV
IAD[15:0] Previous Data Valid after Start of Read
4
10
ns
Figure 27. IDMA Read, Short Read Only Mode
IACK
IS
IR D
tIRDE
tRDV
tIKR
tIKHR
tIKDH
tIKDD
Previous Data
IAD[15:0]
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