參數(shù)資料
型號(hào)： ADSP-21MOD980N-000
廠商： ANALOG DEVICES INC
元件分類： 通信及網(wǎng)絡(luò)
英文描述： CAP 27PF 100V 10% X7R AXIAL BULK M-MIL-PRF-39014
中文描述： SPECIALTY TELECOM CIRCUIT, PBGA352
封裝： 35 X 35 MM, PLASTIC, BGA-352
文件頁(yè)數(shù)： 11/42頁(yè)
文件大?。?/td> 566K
代理商： ADSP-21MOD980N-000
11
REV. PrB
6/2001
For current information contact Analog Devices at (800) ANALOGD
ADSP-21mod980N
PRELIMINARY TECHNICAL DATA
MEMORY MAPPED REGISTERS (NEW TO THE
ADSP-21MOD980N)
The ADSP-21mod980N has three memory mapped regis-
ters that differ from other ADSP-21xx Family DSPs. See
“
Waitstate Control Register
”
on page 11. See
“
Programmable Flag & Composite Select Control Regis-
ter
”
on page 12. See
“
System Control Register
”
on
page 12. The slight modifications to these registers provide
the ADSP-21mod980N
’
s waitstate and BMS control
features.
Figure 5. Data Memory Map
ACCESSIBLE WHEN
DM OVLAY = 8
0x0000 - 0x1FFF
ACCESSIBLE WHEN
DM OVLAY = 7
0x0000 - 0x1FFF
ACCESSIBLE WHEN
DM OVLAY = 6
32 MEMORY
MAPPED
REGISTERS
0x3FFF
INTERNAL
8160 WORDS
DATA MEMORY
ADDR
0x3FE0
0x3FDF
8K INTERNAL
DMOVLAY =
0, 4, 5, 6, 7, 8
0x1FFF
0x2000
ACCESSIBLE WHEN
DM OVLAY = 5
ACCESSIBLE WHEN
DM OVLAY = 4
0x0000 - 0x1FFF
ACCESSIBLE WHEN
DM OVLAY = 0
0x0000 - 0x1FFF
0x0000 - 0x1FFF
DATA MEMORY
ALWAYS
ACCESSIBLE
AT ADDRESS
0x2000 - 0x3FFF
INTERNAL
MEMORY
0x0000 - 0x1FFF
Table 5. DMOVLAY bits
DMOVLAY
Memory
A13
A[12:0]
0, 4, 5, 6, 7, 8
Internal
Not
Applicable
Not
Applicable
.
Figure 6. Waitstate Control Register
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
IOWAIT0
Wait State Mode Select
0 = Normal mode (PWAIT, DWAIT, IOWAIT0-3 = N wait states, ranging from 0 to 7)
1 = 2N+1 mode (PWAIT, DWAIT, IOWAIT0-3 = 2N+1 wait states, ranging from 0 to 15)
DM(0x3FFE)
IOWAIT1
IOWAIT2
IOWAIT3
DWAIT
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