參數(shù)資料
型號(hào)： ADSP-21990BSTZ
廠商： Analog Devices Inc
文件頁(yè)數(shù)： 36/50頁(yè)
文件大?。?/td> 0K
描述： IC DSP CONTROLLER 16BIT 176-LQFP
產(chǎn)品變化通告： Product Discontinuance 27/Oct/2011
標(biāo)準(zhǔn)包裝： 1
系列： ADSP-21xx
類型： 定點(diǎn)
接口： SPI，SSP
時(shí)鐘速率： 160MHz
非易失內(nèi)存： 外部
芯片上RAM： 20kB
電壓 - 輸入/輸出： 3.30V
電壓 - 核心： 2.50V
工作溫度： -40°C ~ 85°C
安裝類型： 表面貼裝
封裝/外殼： 176-LQFP
供應(yīng)商設(shè)備封裝： 176-LQFP（24x24）
包裝： 托盤
ADSP-21990
Rev. A
|
Page 41 of 50
|
August 2007
TEST CONDITIONS
The DSP is tested for output enable, disable, and hold time.
Output Disable Time
Output pins are considered to be disabled when they stop driv-
ing, go into a high impedance state, and start to decay from their
output high or low voltage. The time for the voltage on the bus
to decay by ΔV is dependent on the capacitive load, CL, and the
load current, IL. This decay time can be approximated by the fol-
lowing equation.
The output disable time tDIS is the difference between tMEASURED
and tDECAY as shown in Figure 19. The time tMEASURED is the inter-
val from when the reference signal switches to when the output
voltage decays ΔV from the measured output high or output low
voltage. The tDECAY is calculated with test loads CL and IL, and
with ΔV equal to 0.5 V.
Output Enable Time
Output pins are considered to be enabled when they have made
a transition from a high impedance state to when they start driv-
ing. The output enable time tENA is the interval from when a
reference signal reaches a high or low voltage level to when the
output has reached a specified high or low trip point, as shown
in the Output Enable/Disable diagram (Figure 19). If multiple
pins (such as the data bus) are enabled, the measurement value
is that of the first pin to start driving.
Example System Hold Time Calculation
To determine the data output hold time in a particular system,
first calculate tDECAY using the equation at Output Disable Time
on Page 41. Choose ΔV to be the difference between the
ADSP-21990 output voltage and the input threshold for the
device requiring the hold time. A typical ΔV will be 0.4 V. CL is
the total bus capacitance (per data line), and IL is the total leak-
age or three-state current (per data line). The hold time will be
tDECAY plus the minimum disable time (i.e., tDATRWH for the
write cycle).
Figure 19. Output Enable/Disable
Figure 20. Equivalent Device Loading for AC Measurements (Includes All
Fixtures)
t
DECAY
C
L
V
Δ
I
L
---------------
=
REFERENCE
SIGNAL
tDIS
OUTPUT STARTS
DRIVING
VOH (MEASURED) – V2.0V
VOL (MEASURED) + V1.0V
tMEASURED
VOH (MEASURED)
VOL (MEASURED)
HIGH IMPEDANCE STATE.
TEST CONDITIONS CAUSE THIS VOLTAGE
TO BE APPROXIMATELY 1.5V
OUTPUT STOPS
DRIVING
tDECAY
tENA
1.5V
50pF
TO
OUTPUT
PIN
IOL
IOH
Figure 21. Voltage Reference Levels for AC Measurements (Except Output
Enable/Disable)
INPUT
OR
OUTPUT
1.5V
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