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| 型號： | ADSP-2188MKSTZ-300 |
| 廠商： | Analog Devices Inc |
| 文件頁數(shù)： | 5/40頁 |
| 文件大小： | 0K |
| 描述： | IC DSP CONTROLLER 16BIT 100LQFP |
| 標準包裝： | 1 |
| 系列： | ADSP-21xx |
| 類型： | 定點 |
| 接口： | 主機接口，串行端口 |
| 時鐘速率： | 75MHz |
| 非易失內(nèi)存： | 外部 |
| 芯片上RAM： | 256kB |
| 電壓 - 輸入/輸出： | 3.30V |
| 電壓 - 核心： | 2.50V |
| 工作溫度： | 0°C ~ 70°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 100-LQFP |
| 供應商設(shè)備封裝： | 100-LQFP（14x14） |
| 包裝： | 托盤 |
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REV. 0
ADSP-2188M
–13–
Table IV. DMOVLAY Bits
DMOVLAY
Memory
A13
A12:0
0, 4, 5, 6, 7, 8
Internal
Not Applicable
1
External Overlay 1
0
13 LSBs of Address Between 0x2000 and 0x3FFF
2
External Overlay 2
1
13 LSBs of Address Between 0x2000 and 0x3FFF
ACCESSIBLE WHEN
DMOVLAY = 2
0x0000 –0x1FFF
EXTERNAL
MEMORY
ACCESSIBLE WHEN
DMOVLAY = 1
0x0000 – 0x1FFF
ACCESSIBLE WHEN
DMOVLAY = 8
0x0000 – 0x1FFF
DATA MEMORY
0x0000 – 0x1FFF
ACCESSIBLE WHEN
DMOVLAY = 7
0x0000 – 0x1FFF
INTERNAL
MEMORY
ACCESSIBLE WHEN
DMOVLAY = 6
ACCESSIBLE WHEN
DMOVLAY = 5
ACCESSIBLE WHEN
DMOVLAY = 4
ACCESSIBLE WHEN
DMOVLAY = 0
ALWAYS
ACCESSIBLE
AT ADDRESS
0x2000 – 0x3FFF
0x0000 – 0x1FFF
0x3FFF
0x0000
0x1FFF
0x2000
DATA MEMORY
ADDRESS
8K INTERNAL
DMOVLAY = 0, 4, 5, 6, 7, 8
OR
8K EXTERNAL
DMOVLAY = 1, 2
32 MEMORY
MAPPED
REGISTERS
INTERNAL
8160 WORDS
0x3FE0
0x3FDF
Figure 5. Data Memory Map
Data Memory
Data Memory (Full Memory Mode) is a 16-bit-wide space
used for the storage of data variables and for memory-mapped
control registers. The ADSP-2188M has 56K words on Data
Memory RAM on-chip. Part of this space is used by 32 memory-
mapped registers. Support also exists for up to two 8K external
memory overlay spaces through the external data bus. All internal
accesses complete in one cycle. Accesses to external memory are
timed using the wait states specified by the DWAIT register and
the wait state mode bit.
Data Memory (Host Mode) allows access to all internal memory.
External overlay access is limited by a single external address
line (A0).
Memory Mapped Registers (New to the ADSP-2188M)
The ADSP-2188M has three memory mapped registers that differ
from other ADSP-21xx Family DSPs. The slight modifications
to these registers (Wait State Control, Programmable Flag and
Composite Select Control, and System Control) provide the
ADSP-2188M’s wait state and
BMS control features. Default
bit values at reset are shown; if no value is shown, the bit is unde-
fined at reset. Reserved bits are shown on a grey field. These bits
should always be written with zeros.
DWAIT
IOWAIT3
IOWAIT2
IOWAIT1
IOWAIT0
DM(0x3FFE)
WAITSTATE CONTROL
11
1
11
111
1
15 14 13 12 11 10
9
8
7
6
5
43210
WAIT STATE MODE SELECT
0 = NORMAL MODE (PWAIT, DWAIT, IOWAIT0–3 = N WAIT STATES, RANGING
FROM 0 TO 7)
1 = 2N + 1 MODE (PWAIT, DWAIT, IOWAIT0–3 = 2N + 1 WAIT STATES, RANGING
FROM 0 TO 15)
Figure 6. Wait State Control Register
BMWAIT
CMSSEL
0 = DISABLE
CMS
1 = ENABLE
CMS
DM(0x3FE6)
PFTYPE
0 = INPUT
1 = OUTPUT
(WHERE BIT: 11-IOM, 10-BM, 9-DM, 8-PM)
11
1
0
11
000
0
15 14 13 12 11 10
9
8
7
6
5
43210
PROGRAMMABLE FLAG
AND COMPOSITE SELECT CONTROL
Figure 7. Programmable Flag and Composite Control
Register
RESERVED, ALWAYS
SET TO 0
SPORT0 ENABLE
0 = DISABLE
1 = ENABLE
DM(0x3FFF)
SYSTEM CONTROL
SPORT1 ENABLE
0 = DISABLE
1 = ENABLE
SPORT1 CONFIGURE
0 = FI, FO,
IRQ0, IRQ1, SCLK
1 = SPORT1
DISABLE
BMS
0 = ENABLE
BMS
1 = DISABLE
BMS, EXCEPT WHEN MEMORY
STROBES ARE THREE-STATED
PWAIT
PROGRAM MEMORY
WAIT STATES
00
0
1
00
000
0
1
15 14 13 12 11 10
9
8
7
6
5
43210
NOTE: RESERVED BITS ARE SHOWN ON A GRAY FIELD. THESE BITS SHOULD
ALWAYS BE WRITTEN WITH ZEROS.
RESERVED
SET TO 0
Figure 8. System Control Register
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