Timing Requirements: tBH
參數(shù)資料
型號(hào): ADSP-2188MKSTZ-300
廠商: Analog Devices Inc
文件頁(yè)數(shù): 19/40頁(yè)
文件大?。?/td> 0K
描述: IC DSP CONTROLLER 16BIT 100LQFP
標(biāo)準(zhǔn)包裝: 1
系列: ADSP-21xx
類(lèi)型: 定點(diǎn)
接口: 主機(jī)接口,串行端口
時(shí)鐘速率: 75MHz
非易失內(nèi)存: 外部
芯片上RAM: 256kB
電壓 - 輸入/輸出: 3.30V
電壓 - 核心: 2.50V
工作溫度: 0°C ~ 70°C
安裝類(lèi)型: 表面貼裝
封裝/外殼: 100-LQFP
供應(yīng)商設(shè)備封裝: 100-LQFP(14x14)
包裝: 托盤(pán)
REV. 0
–26–
ADSP-2188M
Parameter
Min
Max
Unit
Bus Request–Bus Grant
Timing Requirements:
tBH
BR Hold after CLKOUT High1
0.25tCK + 2
ns
tBS
BR Setup before CLKOUT Low1
0.25tCK + 10
ns
Switching Characteristics:
tSD
CLKOUT High to
xMS, RD, WR Disable
0.25tCK + 8
ns
tSDB
xMS, RD, WR Disable to BG Low
0
ns
tSE
BG High to xMS, RD, WR Enable
0
ns
tSEC
xMS, RD, WR Enable to CLKOUT High
0.25tCK – 3ns
tSDBH
xMS, RD, WR Disable to BGH Low2
0ns
tSEH
BGH High to xMS, RD, WR Enable2
0ns
NOTES
xMS = PMS, DMS, CMS, IOMS, BMS.
1
BR is an asynchronous signal. If BR meets the setup/hold requirements, it will be recognized during the current clock cycle; otherwise the signal will be recognized on
the following cycle. Refer to the ADSP-2100 Family User’s Manual for
BR/BG cycle relationships.
2
BGH is asserted when the bus is granted and the processor or BDMA requires control of the bus to continue.
CLKOUT
tSD
tSDB
tSE
tSEC
tSDBH
tSEH
tBS
BR
tBH
CLKOUT
PMS, DMS
BMS, RD
WR
BG
BGH
Figure 23. Bus Request–Bus Grant
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