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參數(shù)資料
| 型號： | ADSP-2187LBST-210 |
| 廠商： | ANALOG DEVICES INC |
| 元件分類： | 數(shù)字信號處理 |
| 英文描述： | DSP Microcomputer |
| 中文描述： | 24-BIT, 26.3 MHz, OTHER DSP, PQFP100 |
| 封裝： | MS-026BED, LQFP-100 |
| 文件頁數(shù)： | 7/32頁 |
| 文件大?。?/td> | 223K |
| 代理商： | ADSP-2187LBST-210 |
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ADSP-2187L
–7–
REV. 0
1/2x OR
CRYSTAL
SERIAL
SERIAL
SCLK1
IRQ0
IRQ1
TFS1 OR
SPORT1
SCLK0
SPORT0
A0–A21
DATA
CS
BYTE
MEMORY
I/O SPACE
(PERIPHERALS)
2048 LOCATIONS
CS
DATA
ADDR
DATA
ADDR
OVERLAY
MEMORY
PM TWO 8K
DTWO 8K
D
23-0
A
13-0
D
23-8
A
10-0
D
15-8
D
23-16
A
13-0
14
24
FL0-2
CLKIN
XTAL
ADDR13-0
DATA23-0
BMS
IOMS
PMS
BBR
PWPWD
ADSP-2187L
1/2x OR
CRYSTAL
SERIAL
SERIAL
ISYOR
m
CONTROLLER
16
1
16
SCLK1
IRQ0
IRQ1
TFS1 OR
SPORT1
SCLK0
SPORT0
IRD
/D6
IWR
/D7
IACK
/D3
IAD15-0
IDMA PORT
FL0-2
CLKIN
XTAL
A0
DATA23-8
BMS
IOMS
PMS
DMS
CMS
BR
BG
BGH
PWD
PWDACK
ADSP-2187L
/PF4
IRQ2
IRQL0
/PF5
IRQL1
/PF6
MODE D/PF3
MODE C/PF2
MODE B/PF1
HOST MEMORY MODE
IRQ2
/PF7
IRQE
/PF4
IRQL0
/PF5
IRQL1
/PF6
MODE D/PF3
MODE C/PF2
MODE A/PF0
MODE B/PF1
FULL MEMORY MODE
WR
RD
WR
RD
Figure 2. ADSP-2187L Basic System Configuration
The ADSP-2187L uses an input clock with a frequency equal to
half the instruction rate; a 26.00 MHz input clock yields a 19 ns
processor cycle (which is equivalent to 52 MHz). Normally, in-
structions are executed in a single processor cycle. All device tim-
ing is relative to the internal instruction clock rate, which is
indicated by the CLKOUT signal when enabled.
Because the ADSP-2187L includes an on-chip oscillator circuit,
an external crystal may be used. The crystal should be connected
across the CLKIN and XTAL pins, with two capacitors connected
as shown in Figure 3. Capacitor values are dependent on crystal
type and should be specified by the crystal manufacturer. A
parallel-resonant, fundamental frequency, microprocessor-grade
crystal should be used.
A clock output (CLKOUT) signal is generated by the processor
at the processor’s cycle rate. This can be enabled and disabled
by the CLK0DIS bit in the SPORT0 Autobuffer Control Register.
CLKIN
CLKOUT
XTAL
DSP
Figure 3. External Crystal Connections
Reset
The
RESET
signal initiates a master reset of the ADSP-2187L.
The
RESET
signal must be asserted during the power-up se-
quence to assure proper initialization.
RESET
during initial
power-up must be held long enough to allow the internal clock
to stabilize. If
RESET
is activated any time after power-up, the
clock continues to run and does not require stabilization time.
The power-up sequence is defined as the total time required for
the crystal oscillator circuit to stabilize after a valid V
DD
is ap-
plied to the processor, and for the internal phase-locked loop
(PLL) to lock onto the specific crystal frequency. A minimum
of 2000 CLKIN cycles ensures that the PLL has locked, but
does not include the crystal oscillator start-up time. During this
power-up sequence the
RESET
signal should be held low. On
any subsequent resets, the
RESET
signal must meet the mini-
mum pulsewidth specification, t
RSP
.
The
RESET
input contains some hysteresis; however, if an
RC circuit is used to generate the
RESET
signal, an external
Schmidt trigger is recommended.
The master reset sets all internal stack pointers to the empty
stack condition, masks all interrupts and clears the MSTAT
register. When
RESET
is released, if there is no pending bus
request and the chip is configured for booting, the boot-loading
sequence is performed. The first instruction is fetched from
on-chip program memory location 0x0000 once boot loading
completes.
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| ADSP-2187LBSTZ-160 | 制造商:Analog Devices 功能描述:DSP FIX PT 16BIT 40MHZ 40MIPS 100LQFP - Trays |
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| ADSP-2187LBSTZ-210 | 功能描述:IC DSP CONTROLLER 16BIT 100-TQFP RoHS:是 類別:集成電路 (IC) >> 嵌入式 - DSP（數(shù)字式信號處理器） 系列:ADSP-21xx 標(biāo)準包裝:2 系列:StarCore 類型:SC140 內(nèi)核 接口:DSI，以太網(wǎng)，RS-232 時鐘速率:400MHz 非易失內(nèi)存:外部 芯片上RAM:1.436MB 電壓 - 輸入/輸出:3.30V 電壓 - 核心:1.20V 工作溫度:-40°C ~ 105°C 安裝類型:表面貼裝 封裝/外殼:431-BFBGA，F(xiàn)CBGA 供應(yīng)商設(shè)備封裝:431-FCPBGA（20x20） 包裝:托盤 |
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