參數(shù)資料
型號: ADSP-2189NKST-320
廠商: ANALOG DEVICES INC
元件分類: 數(shù)字信號處理
英文描述: DSP Microcomputer
中文描述: 24-BIT, 40 MHz, OTHER DSP, PQFP100
封裝: MS-026BED, LQFP-100
文件頁數(shù): 1/32頁
文件大?。?/td> 244K
代理商: ADSP-2189NKST-320
REV. A
Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties
which may result from its use. No license is granted by implication or
otherwise under any patent or patent rights of Analog Devices.
a
ADSP-2189M
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781/329-4700
World Wide Web Site: http://www.analog.com
Fax: 781/326-8703
Analog Devices, Inc., 2000
DSP Microcomputer
FUNCTIONAL BLOCK DIAGRAM
SERIAL PORTS
SPORT 1
SPORT 0
MEMORY
PROGRI/O
FAND
CBYTE DMA
MEMORY
32K
M48K
16 BIT
TIMER
ARCHITECTURE
SHIFTER
MAC
ALU
ARITHMETIC UNITS
PCONTROL
PROGRAM
DAG 2
DAG 1
GENERATORS
PROGRAM MEMORY ADDRESS
DATA MEMORY ADDRESS
PROGRAM MEMORY DATA
DATA MEMORY DATA
EXDATA
BUS
ADDRESS
BUS
INDMA
PORT
EXDATA
BUS
OR
FUL MODE
HOST MODE
GENERAL DESCRIPTION
The ADSP-2189M is a single-chip microcomputer optimized
for digital signal processing (DSP) and other high speed nu-
meric processing applications.
The ADSP-2189M combines the ADSP-2100 family base archi-
tecture (three computational units, data address generators and
a program sequencer) with two serial ports, a 16-bit internal
DMA port, a byte DMA port, a programmable timer, Flag I/O,
extensive interrupt capabilities, and on-chip program and data
memory.
The ADSP-2189M integrates 192K bytes of on-chip memory
configured as 32K words (24-bit) of program RAM and 48K
words (16-bit) of data RAM. Power-down circuitry is also pro-
vided to meet the low power needs of battery operated portable
equipment. The ADSP-2189M is available in a 100-lead LQFP
package.
In addition, the ADSP-2189M supports new instructions, which
include bit manipulations—bit set, bit clear, bit toggle, bit test—
new ALU constants, new multiplication instruction (x squared),
biased rounding, result free ALU operations, I/O memory trans-
fers and global interrupt masking, for increased flexibility.
FEATURES
PERFORMANCE
13.3 ns Instruction Cycle Time @ 2.5 Volts (Internal),
75 MIPS Sustained Performance
Single-Cycle Instruction Execution
Single-Cycle Context Switch
3-Bus Architecture Allows Dual Operand Fetches in
Every Instruction Cycle
Multifunction Instructions
Power-Down Mode Featuring Low CMOS Standby
Power Dissipation with 200 CLKIN Cycle Recovery
from Power-Down Condition
Low Power Dissipation in Idle Mode
INTEGRATION
ADSP-2100 Family Code Compatible (Easy to Use Alge-
braic Syntax), with Instruction Set Extensions
192K Bytes of On-Chip RAM, Configured as 32K Words
On-Chip Program Memory RAM and 48K Words On-
Chip Data Memory RAM
Dual Purpose Program Memory for Both Instruction
and Data Storage
Independent ALU, Multiplier/Accumulator and Barrel
Shifter Computational Units
Two Independent Data Address Generators
Powerful Program Sequencer Provides Zero Overhead
Looping Conditional Instruction Execution
Programmable 16-Bit Interval Timer with Prescaler
100-Lead LQFP
SYSTEM INTERFACE
Flexible I/O Structure Allows 2.5 V or 3.3 V Operation;
All Inputs Tolerate Up to 3.6 V, Regardless of Mode
16-Bit Internal DMA Port for High Speed Access to On-
Chip Memory (Mode Selectable)
4 MByte Memory Interface for Storage of Data Tables
and Program Overlays (Mode Selectable)
8-Bit DMA to Byte Memory for Transparent Program
and Data Memory Transfers (Mode Selectable)
I/O Memory Interface with 2048 Locations Supports
Parallel Peripherals (Mode Selectable)
Programmable Memory Strobe and Separate I/O
Memory Space Permits “Glueless” System Design
Programmable Wait-State Generation
Two Double-Buffered Serial Ports with Companding
Hardware and Automatic Data Buffering
Automatic Booting of On-Chip Program Memory from
Byte-Wide External Memory, e.g., EPROM, or
Through Internal DMA Port
Six External Interrupts
13 Programmable Flag Pins Provide Flexible System
Signaling
UART Emulation through Software SPORT Reconfiguration
ICE-Port Emulator Interface Supports Debugging in
Final Systems
ICE-Port is a trademark of Analog Devices, Inc.
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