參數(shù)資料
型號(hào)： ADSP-2186BSTZ-160
廠商： Analog Devices Inc
文件頁(yè)數(shù)： 36/36頁(yè)
文件大?。?/td> 0K
描述： IC DSP CONTROLLER 16BIT 100LQFP
標(biāo)準(zhǔn)包裝： 1
系列： ADSP-21xx
類型： 定點(diǎn)
接口： 主機(jī)接口，串行端口
時(shí)鐘速率： 40MHz
非易失內(nèi)存： 外部
芯片上RAM： 40kB
電壓 - 輸入/輸出： 5.00V
電壓 - 核心： 5.00V
工作溫度： -40°C ~ 85°C
安裝類型： 表面貼裝
封裝/外殼： 100-LQFP
供應(yīng)商設(shè)備封裝： 100-LQFP（14x14）
包裝： 托盤
ADSP-2186
–9–
REV. B
There are 8160 words of memory accessible internally when the
DMOVLAY register is set to 0. When DMOVLAY is set to
something other than 0, external accesses occur at addresses
0x0000 through 0x1FFF. The external address is generated as
shown in Table III.
Table III. Addressing
DMOVLAY Memory
A13
A12:0
0
Reserved
Not Applicable Not Applicable
1
External
13 LSBs of Address
Overlay 1
0
Between 0x0000
and 0x1FFF
2
External
13 LSBs of Address
Overlay 2
1
Between 0x0000
and 0x1FFF
This organization allows for two external 8K overlays using only
the normal 14 address bits. All internal accesses complete in one
cycle. Accesses to external memory are timed using the wait states
specified by the DWAIT register.
I/O Space (Full Memory Mode)
The ADSP-2186 supports an additional external memory space
called I/O space. This space is designed to support simple con-
nections to peripherals or to bus interface ASIC data registers.
I/O space supports 2048 locations. The lower eleven bits of the
external address bus are used; the upper three bits are undefined.
Two instructions were added to the core ADSP-2100 Family
instruction set to read from and write to I/O memory space. The
I/O space also has four dedicated three-bit wait state registers,
IOWAIT0-3, that specify up to seven wait states to be automati-
cally generated for each of four regions. The wait states act on
address ranges as shown in Table IV.
Table IV.
Address Range
Wait State Register
0x000–0x1FF
IOWAIT0
0x200–0x3FF
IOWAIT1
0x400–0x5FF
IOWAIT2
0x600–0x7FF
IOWAIT3
Composite Memory Select (
CMS)
The ADSP-2186 has a programmable memory select signal that
is useful for generating memory select signals for memories
mapped to more than one space. The
CMS signal is generated
to have the same timing as each of the individual memory select
signals (
PMS, DMS, BMS, IOMS), but can combine their
functionality.
Each bit in the CMSSEL register, when set, causes the
CMS
signal to be asserted when the selected memory select is asserted.
For example, to use a 32K word memory to act as both program
and data memory, set the
PMS and DMS bits in the CMSSEL
register and use the
CMS pin to drive the chip select of the
memory and use either
DMS or PMS as the additional address bit.
The
CMS pin functions as the other memory select signals, with
the same timing and bus request logic. A 1 in the enable bit
causes the assertion of the
CMS signal at the same time as the
selected memory select signal. All enable bits, except the
BMS
bit, default to 1 at reset.
Boot Memory Select (
BMS) Disable
The ADSP-2186 also lets you boot the processor from one
external memory space while using a different external memory
space for BDMA transfers during normal operation. You can
use the
CMS to select the first external memory space for BDMA
transfers and
BMS to select the second external memory space
for booting. The
BMS signal can be disabled by setting Bit 3 of
the System Control Register to 1. The System Control Register
is illustrated in Figure 7.
SYSTEM CONTROL REGISTER
PWAIT
PROGRAM MEMORY
WAIT STATES
BMS ENABLE
0 = ENABLED,
1 = DISABLED
DM (0 3FFF)
00
0
1
00
000
0
1
15 14 13 12 11 10
9
8
7
6
5
43210
SPORT0 ENABLE
1 = ENABLED,
0 = DISABLED
SPORT1 ENABLE
1 = ENABLED,
0 = DISABLED
SPORT1 CONFIGURE
1 = SERIAL PORT
0 = FI, FO,
IRQ0, IRQ1, SCLK
RESERVED
SET TO ZERO
RESERVED
SET TO ZERO
Figure 7. System Control Register
Byte Memory
The byte memory space is a bidirectional, 8-bit-wide, external
memory space used to store programs and data. Byte memory is
accessed using the BDMA feature. The BDMA Control Register is
shown in Figure 8. The byte memory space consists of 256 pages,
each of which is 16K
× 8.
BDMA CONTROL
BMPAGE
BTYPE
BDIR
0 = LOAD FROM BM
1 = STORE TO BM
BCR
0 = RUN DURING BDMA
1 = HALT DURING BDMA
00
0
00
000
0
1
0
15 14 13 12 11 10
9
8
7
6
5
43210
DM (0 3FE3)
RESERVED
SET TO ZERO
Figure 8. BDMA Control Register
The byte memory space on the ADSP-2186 supports read and
write operations as well as four different data formats. The byte
memory uses data bits 15:8 for data. The byte memory uses
data bits 23:16 and address bits 13:0 to create a 22-bit address.
This allows up to a 4 meg
× 8 (32 megabit) ROM or RAM to be
used without glue logic. All byte memory accesses are timed by
the BMWAIT register.
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