參數(shù)資料
型號(hào)： ADSP-2171BSTZ-133
廠商： Analog Devices Inc
文件頁數(shù)： 7/52頁
文件大小： 0K
描述： IC DSP CONTROLLER 16BIT 128TQFP
產(chǎn)品變化通告： Product Discontinuance 27/Oct/2011
Mold Change 11/Jul/2012
標(biāo)準(zhǔn)包裝： 1
系列： ADSP-21xx
類型： 定點(diǎn)
接口： 主機(jī)接口，串行端口
時(shí)鐘速率： 33MHz
非易失內(nèi)存： 外部
芯片上RAM： 10kB
電壓 - 輸入/輸出： 5.00V
電壓 - 核心： 5.00V
工作溫度： -40°C ~ 85°C
安裝類型： 表面貼裝
封裝/外殼： 128-LQFP
供應(yīng)商設(shè)備封裝： 128-TQFP（14x20）
包裝： 托盤
ADSP-2171/ADSP-2172/ADSP-2173
REV. A
–15–
Control Registers
INSTRUCTION SET DESCRIPTION
The ADSP-217x assembly language instruction set has an alge-
braic syntax that was designed for ease of coding and read-
ability. The assembly language, which takes full advantage of
the processor’s unique architecture, offers the following benefits:
The algebraic syntax eliminates the need to remember cryptic
assembler mnemonics. For example, a typical arithmetic add
instruction, such as AR = AX0 + AY0, resembles a simple
equation.
Every instruction assembles into a single, 24-bit word that can
execute in a single instruction cycle.
The syntax is a superset ADSP-2100 Family assembly lan-
guage and is completely source and object code compatible
with other family members. Programs may need to be relo-
cated to utilize internal memory and conform to the ADSP-
217x’s interrupt vector and reset vector map.
Sixteen condition codes are available. For conditional jump,
call, return, or arithmetic instructions, the condition can be
checked and the operation executed in the same instruction
cycle.
Multifunction instructions allow parallel execution of an arith-
metic instruction with up to two fetches or one write to pro-
cessor memory space during a single instruction cycle.
Consult the ADSP-2100 Family User’s Manual for a complete
description of the syntax and an instruction set reference.
Biased Rounding
A new mode allows biased rounding in addition to the normal
unbiased rounding. When the BIASRND bit is set to 0, the nor-
mal unbiased rounding operations occur. When the BIASRND
bit is set to 1, biased rounding occurs instead of the normal un-
biased rounding. When operating in biased rounding mode all
rounding operations with MR0 set to 0x8000 will round up,
rather than only rounding odd MR1 values up. For example:
MR value before RND
biased RND result unbiased RND result
00-0000-8000
00-0001-8000
00-0000-8000
00-0001-8000
00-0002-8000
00-0000-8001
00-0001-8001
00-0002-8001
00-0000-7FFF
00-0001-7FFF
This mode only has an effect when the MR0 register contains
0x8000, all other rounding operation work normally. This mode
was added to allow more efficient implementation of bit speci-
fied algorithms which specify biased rounding such as the GSM
speech compression routines. Unbiased rounding is preferred
for most algorithms.
Note: BIASRND bit is Bit 12 of the SPORT0 Autobuffer
Control register.
HSR6
15
14
13
12
11
10
9
8765
432
10
0
00
0
Host HDR0 Write
Host HDR1 Write
Host HDR2 Write
Host HDR3 Write
Host HDR4 Write
Host HDR5 Write
2171 HDR5 Write
2171 HDR4 Write
2171 HDR3 Write
2171 HDR2 Write
2171 HDR1 Write
2171 HDR0 Write
Overwrite Mode
Software Reset
HSR7
15
14
13
12
11
10
9
8765
4321
0
00
0
1
2171 HDR0 Write
2171 HDR1 Write
2171 HDR2 Write
2171 HDR3 Write
2171 HDR4 Write
2171 HDR5 Write
0x3FE6
0x3FE7
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