參數(shù)資料
型號: ADSP-2171BSTZ-133
廠商: Analog Devices Inc
文件頁數(shù): 50/52頁
文件大?。?/td> 0K
描述: IC DSP CONTROLLER 16BIT 128TQFP
產(chǎn)品變化通告: Product Discontinuance 27/Oct/2011
Mold Change 11/Jul/2012
標準包裝: 1
系列: ADSP-21xx
類型: 定點
接口: 主機接口,串行端口
時鐘速率: 33MHz
非易失內(nèi)存: 外部
芯片上RAM: 10kB
電壓 - 輸入/輸出: 5.00V
電壓 - 核心: 5.00V
工作溫度: -40°C ~ 85°C
安裝類型: 表面貼裝
封裝/外殼: 128-LQFP
供應(yīng)商設(shè)備封裝: 128-TQFP(14x20)
包裝: 托盤
ADSP-2171/ADSP-2172/ADSP-2173
REV. A
–7–
Figure 3. ADSP-217x Basic System Configuration
Because the ADSP-217x includes an on-chip oscillator circuit,
an external crystal may be used. The crystal should be con-
nected across the CLKIN and XTAL pins, with two capacitors
connected as shown in Figure 4. A parallel-resonant, fundamen-
tal frequency, microprocessor-grade crystal should be used.
CLKIN
CLKOUT
XTAL
ADSP-217x
Figure 4. External Crystal Connections
A clock output (CLKOUT) signal is generated by the processor
at the processor’s cycle rate. This can be enabled and disabled
by the CLKODIS bit in the SPORT0 Autobuffer Control Reg-
ister, DM[0x3FF3].
Reset
The RESET signal initiates a master reset of the ADSP-217x.
The RESET signal must be asserted during the power-up se-
quence to assure proper initialization. RESET during initial
power-up must be held long enough to allow the internal clock
SCLK
RFS
TFS
DT
DR
ADSP-217x
CLKIN
CLKOUT
V
DD
SERIAL
PORT 0
GND
SERIAL
PORT 1
DATA
ADDRESS
PMS
DMS
BMS
RD
WR
14
24
16
8
24
SERIAL DEVICE
14
2
XTAL
MMAP
BG
BR
IRQ2
RESET
SCLK
RFS or IRQ0
TFS or IRQ1
DT or FO
DR or FI
AD
CS
DATA MEMORY
&
PERIPHERALS
A
D
CS
OE
WE
PROGRAM
MEMORY
(OPTIONAL)
NOTE:
THE TWO MSBs OF THE DATA BUS ARE USED AS THE MSBs OF THE BOOT EPROM ADDRESS.
THIS IS ONLY REQUIRED FOR THE 27C256 AND 27C512.
A
D
BOOT MEMORY
SERIAL DEVICE
(OPTIONAL)
D
15-8
e.g., EPROM
27C64
27C128
27C256
27C512
HOST
MODE
FL2-0
4
6
97
16
HOST
PROCESSOR
(OPTIONAL)
3
HIP CONTROL
HIP
HIP DATA/ADDR
PWDACK
PWD
CLOCK OR
CRYSTAL
D
23-22
D
23-8
OE
WE
OE
CS
(OPTIONAL)
to stabilize. If RESET is activated any time after power-up, the
clock continues to run and does not require stabilization time.
The power-up sequence is defined as the total time required for
the crystal oscillator circuit to stabilize after a valid VDD is ap-
plied to the processor, and for the internal phase-locked loop
(PLL) to lock onto the specific crystal frequency. A minimum of
2000 CLKIN cycles ensures that the PLL has locked but does
not include the crystal oscillator start-up time. During this
power-up sequence the RESET signal should be held low. On
any subsequent resets, the RESET signal must meet the mini-
mum pulse width specification, tRSP.
The RESET input contains some hysteresis; however, if you use
an RC circuit to generate your RESET signal, the use of an ex-
ternal Schmidt trigger is recommended.
The master reset sets all internal stack pointers to the empty
stack condition, masks all interrupts and clears the MSTAT reg-
ister. When RESET is released, if there is no pending bus re-
quest and the chip is configured for booting (MMAP = 0), the
boot-loading sequence is performed. Then the first instruction is
fetched from internal program memory location 0x0000.
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