參數(shù)資料
型號： ADSP-2171BSTZ-133
廠商： Analog Devices Inc
文件頁數(shù)： 34/52頁
文件大?。?/td> 0K
描述： IC DSP CONTROLLER 16BIT 128TQFP
產(chǎn)品變化通告： Product Discontinuance 27/Oct/2011
Mold Change 11/Jul/2012
標(biāo)準(zhǔn)包裝： 1
系列： ADSP-21xx
類型： 定點
接口： 主機(jī)接口，串行端口
時鐘速率： 33MHz
非易失內(nèi)存： 外部
芯片上RAM： 10kB
電壓 - 輸入/輸出： 5.00V
電壓 - 核心： 5.00V
工作溫度： -40°C ~ 85°C
安裝類型： 表面貼裝
封裝/外殼： 128-LQFP
供應(yīng)商設(shè)備封裝： 128-TQFP（14x20）
包裝： 托盤
REV. A
–4–
ADSP-2171/ADSP-2172/ADSP-2173
Pin Description
The ADSP-217x is available in 128-lead TQFP and 128-lead
PQFP packages. Table I contains the pin descriptions.
Table I. ADSP-217x Pin List
Pin
#
Group
of
Input/
Name
Pins Output Function
Address
14
O
Address output for program,
data and boot memory spaces
Data
24
I/O
Data I/O pins for program
and data memories. Input
only for boot memory space,
with two MSBs used as boot
space addresses.
RESET
1
I
Processor reset input
IRQ2
1
I
External interrupt request #2
BR
1
I
External bus request input
BG
1
O
External bus grant output
BGH
1
O
External bus grant hang output
PMS
1
O
External program memory select
DMS
1
O
External data memory select
BMS
1
O
Boot memory select
RD
1
O
External memory read enable
WR
1
O
External memory write enable
MMAP
1
I
Memory map select
CLKIN,
XTAL
2
I
External clock or quartz crystal
input
CLKOUT
1
O
Processor clock output
HSEL
1
I
HIP select input
HACK
1
O
HIP acknowledge output
HSIZE
1
8/16 bit host select input
0 = 16-bit; 1 = 8-bit
BMODE
1
I
Boot mode select input
0 = EPROM/data bus; 1 = HIP
HMD0
1
I
Bus strobe select input
0 = RD, WR; 1 = RW, DS
HMD1
1
I
HIP address/data mode select
input 0 = separate; 1 =
multiplexed
HRD
/HRW
1
I
HIP read strobe/read/write
select input
HWR
/HDS
1
I
HIP write strobe/host data
strobe select input
HD15–0/
HAD15-0
16
I/O
HIP data/data and address
HA2/ALE
1
I
Host address 2/Address latch
enable input
HA1–0/
Unused
2
I
Host addresses 1 and 0 inputs
SPORT0
5
I/O
Serial port 0 I/O pins (TFS0,
RFS0, DT0, DR0, SCLK0)
SPORT1
5
I/O
Serial port 1 I/O pins
or
IRQ1
(TFS1) 1
I
External interrupt request #1
IRQ0
(RFS1) 1
I
External interrupt request #0
SCLK1
1
O
Programmable clock output
FO (DT1)
1
O
Flag Output pin
FI (DR1)
1
I
Flag Input pin
FL2–0
3
O
General purpose flag output
pins
VDD
6
Power supply pins
GND
11
Ground pins
PWD
1
I
Powerdown pin
PWDACK
1
O
Powerdown acknowledge pin
Host Interface Port
The ADSP-217x host interface port is a parallel I/O port that al-
lows for an easy connection to a host processor. Through the
HIP, the ADSP-217x can be used as a memory-mapped periph-
eral to a host computer. The HIP can be thought of as an area
of dual-ported memory, or mailbox registers, that allow commu-
nication between the computational core of the ADSP-217x and
the host computer.
The HIP is completely asynchronous. The host processor can
write data into the HIP while the ADSP-217x is operating at full
speed.
The HIP can be configured with the following pins:
HSIZE configures HIP for 8-bit or 16-bit communication with
the host processor.
BMODE (when MMAP = 0) determines whether the ADSP-
217x boots from the host processor (through the HIP) or ex-
ternal EPROM (through the data bus).
HMD0 configures the bus strobes as separate read and write
strobes, or a single read/write select and a host data strobe.
HMD1 selects separate address (3-bit) and data (16-bit)
buses, or a multiplexed, 16-bit address/data bus with address
latch enable.
Tying these pins to appropriate values configures the ADSP-
217x for straight-wire interface to a variety of industry-standard
microprocessors and microcomputers.
In 8-bit reads, the ADSP-217x three-states the upper eight bits
of the bus. When the host processor writes an 8-bit value to the
HIP, the upper eight bits are all zeros. For additional informa-
tion refer to the ADSP-2100 Family User’s Manual.
HIP Operation
The HIP contains six data registers (HDR5–0) and two status
registers (HSR7–6) with an associated HMASK register for
masking interrupts from individual HIP data registers. All HIP
data registers are memory-mapped into the internal data
memory of the ADSP-217x. HIP transfers can be managed us-
ing either interrupts or a polling scheme. These registers are
shown in the section “ADSP-217x Registers.”
The HIP allows a software reset to be performed by the host
processor. The internal software reset signal is asserted for five
ADSP-217x processor cycles.
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