參數(shù)資料
型號: ADSP-21371KSWZ-2B
廠商: Analog Devices Inc
文件頁數(shù): 37/48頁
文件大?。?/td> 0K
描述: IC DSP 32BIT 266MHZ 208-LQFP
產(chǎn)品培訓模塊: SHARC Processor Overview
標準包裝: 1
系列: SHARC®
類型: 浮點
接口: DAI,DPI
時鐘速率: 266MHz
非易失內(nèi)存: ROM(512 kB)
芯片上RAM: 128kB
電壓 - 輸入/輸出: 3.30V
電壓 - 核心: 1.20V
工作溫度: 0°C ~ 70°C
安裝類型: 表面貼裝
封裝/外殼: 208-LQFP 裸露焊盤
供應(yīng)商設(shè)備封裝: 208-LQFP-EP(28x28)
包裝: 托盤
ADSP-21371
TWI Controller Timing
Table 40 and Figure 32 provide timing information for the TWI
interface. Input Signals (SCL, SDA) are routed to the
DPI_P14–1 pins using the SRU. Therefore, the timing specifica
tions provided below are valid at the DPI_P14–1 pins.
Table 40. Characteristics of the SDA and SCL Bus Lines for F/S-Mode TWI Bus Devices1
Parameter
Min
Standard Mode
Max
Min
Fast Mode
Max
Unit
fSCL
SCL Clock Frequency
0
100
0
400
kHz
tHDSTA
Hold Time (repeated) Start Condition. After This
Period, the First Clock Pulse is Generated.
4.0
0.6
μs
tLOW
Low Period of the SCL Clock
4.7
1.3
μs
tHIGH
High Period of the SCL Clock
4.0
0.6
μs
tSUSTA
Setup Time for a Repeated Start Condition
4.7
0.6
μs
tHDDAT
Data Hold Time for TWI-bus Devices
0
μs
tSUDAT
Data Setup Time
250
100
ns
tSUSTO
Setup Time for Stop Condition
4.0
0.6
μs
tBUF
Bus Free Time Between a Stop and Start Condition
4.7
1.3
μs
tSP
Pulse Width of Spikes Suppressed By the Input Filter n/a
n/a
0
50
ns
1 All values referred to VIHmin and VILmax levels. For more information, see Electrical Characteristics on page 15.
DPI_P14-1
SDA
DPI_P14-1
SCL
t
LOW
tHIGH
t
HDS TA
tHDDAT
t
SUDA T
t SUSTO
S
t
SU S TA
Sr
t SP
t
HDS TA
P
S
tBUF
Figure 32. Fast and Standard Mode Timing on the TWI Bus
Rev. 0
|
Page 42 of 48
|
June 2007
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