參數(shù)資料
型號: ADSP-21371KSWZ-2B
廠商: Analog Devices Inc
文件頁數(shù): 26/48頁
文件大?。?/td> 0K
描述: IC DSP 32BIT 266MHZ 208-LQFP
產(chǎn)品培訓(xùn)模塊: SHARC Processor Overview
標(biāo)準(zhǔn)包裝: 1
系列: SHARC®
類型: 浮點
接口: DAI,DPI
時鐘速率: 266MHz
非易失內(nèi)存: ROM(512 kB)
芯片上RAM: 128kB
電壓 - 輸入/輸出: 3.30V
電壓 - 核心: 1.20V
工作溫度: 0°C ~ 70°C
安裝類型: 表面貼裝
封裝/外殼: 208-LQFP 裸露焊盤
供應(yīng)商設(shè)備封裝: 208-LQFP-EP(28x28)
包裝: 托盤
ADSP-21371
DAI_P20-1
(SCLK)
DAI_P20-1
(FS)
DAI_P20-1
(DATA CHANNEL A/B)
DAI_P20-1
(SCLK)
DAI_P20-1
(FS)
DAI_P20-1
(DATA CHANNEL A/B)
EXTERNAL RECEIVE FS WITH MCE = 1, MFD = 0
DRIVE
SAMPLE
DRIVE
SAMPLE
DRIVE
LATE EXTERNAL TRANSMIT FS
1ST BIT
2ND BIT
1ST BIT
2ND BIT
tHFSE/I
tSFSE/I
tDDTE/I
tDDTENFS
tDDTLFSE
tHDTE/I
tSFSE/I
tDDTE/I
tDDTENFS
tDDTLFSE
tHDTE/I
tHFSE/I
NOTE: SERIAL PORT SIGNALS (SCLK, FS, DATA CHANNEL A/B) ARE ROUTED TO THE DAI_P20-1PINS
USING THE SRU. THE TIMING SPECIFICATIONS PROVIDED HERE ARE VALID AT THE DAI_P20-1PINS.
THE CHARACTERIZED AC SPORT TIMINGS ARE APPLICABLE WHEN INTERNAL CLOCKS AND FRAMES
ARE LOOPED BACK FROM THE PIN, NOT ROUTED DIRECTLY THROUGH SAU.
Figure 20. External Late Frame Sync1
1 This figure reflects changes made to support left-justified sample pair mode.
Rev. 0
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Page 32 of 48
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June 2007
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