參數(shù)資料
型號(hào): ADSP-21266SKSTZ-2D
廠商: ANALOG DEVICES INC
元件分類(lèi): 數(shù)字信號(hào)處理
英文描述: SHARC Embedded Processor
中文描述: 16-BIT, 66.67 MHz, OTHER DSP, PQFP144
封裝: ROHS COMPLIANT, MS-026BFB, LQFP-144
文件頁(yè)數(shù): 21/44頁(yè)
文件大?。?/td> 426K
代理商: ADSP-21266SKSTZ-2D
ADSP-21266
Rev. B
|
Page 21 of 44
|
May 2005
Timer PWM_OUT Cycle Timing
The timing specification in
Table 15
and
Figure 12
applies to
Timer in PWM_OUT (pulse-width modulation) mode. Timer
signals are routed to the DAI_P20
1 pins through the SRU.
Therefore, the timing specifications provided below are valid at
the DAI_P20
1 pins.
Timer WDTH_CAP Timing
The timing specification in
Table 16
and
Figure 13
applies to
Timer in WDTH_CAP (pulse width count and capture) mode.
Timer signals are routed to the DAI_P20
1 pins through the
SRU. Therefore, the timing specifications provided below are
valid at the DAI_P20
1 pins.
Table 15. Timer PWM_OUT Timing
Parameter
Switching Characteristic
t
PWMO
Min
Max
Unit
Timer Pulse Width Output
2 t
CCLK
– 1
2(2
31
– 1) t
CCLK
ns
Figure 12. Timer PWM_OUT Timing
DAI_P20–1
(TIMER)
t
PWMO
Table 16. Timer Width Capture Timing
Parameter
Timing Requirement
t
PWI
Min
Max
Unit
Timer Pulse Width
2 t
CCLK
2(2
31
– 1) t
CCLK
ns
Figure 13. Timer Width Capture Timing
DAI_P20–1
(TIMER)
t
PWI
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