參數(shù)資料
型號： ADSP-21161NKCA-100
廠商： ANALOG DEVICES INC
元件分類： 數(shù)字信號處理
英文描述： DSP Microcomputer
中文描述： 48-BIT, 27.5 MHz, OTHER DSP, PBGA225
封裝： 17 X 17 MM, MO-192AAF-2, BGA-225
文件頁數(shù)： 37/60頁
文件大?。?/td> 1019K
代理商： ADSP-21161NKCA-100
–37–
REV. A
ADSP-21161N
DMA Handshake
These specifications describe the three DMA handshake modes.
In all three modes
DMAR
is used to initiate transfers. For
handshake mode,
DMAG
controls the latching or enabling of
data externally. For external handshake mode, the data transfer
is controlled by the ADDR23–0,
RD
,
WR
,
MS3–0
, ACK, and
DMAG
signals. For Paced Master mode, the data transfer is
controlled by ADDR23–0,
RD
,
WR
,
MS3–0
, and ACK (not
DMAG
). For Paced Master mode, the Memory Read-Bus
Master, Memory Write-Bus Master, and Synchronous
Read/Write-Bus Master timing specifications for ADDR23
–
0,
RD
,
WR
,
MS3–0
, DATA47
–
16, and ACK also apply.
Table 24. DMA Handshake
Parameter
Timing Requirements
t
SDRC
t
WDR
t
SDATDGL
t
HDATIDG
t
DATDRH
t
DMARLL
t
DMARH
Min
Max
Unit
DMARx
Setup Before CLKIN
1
DMARx
Width Low (Nonsynchronous)
2
Data Setup After
DMAGx
Low
3
Data Hold After
DMAGx
High
Data Valid After
DMARx
High
3
DMARx
Low Edge to Low Edge
4
DMARx
Width High
2
3.5
t
CCLK
+4.5
ns
ns
ns
ns
ns
ns
ns
t
CKOP
–0.5t
CCLK
–7
2
t
CKOP
+3
t
CKOP
t
CCLK
+4.5
Switching Characteristics
t
DDGL
t
WDGH
t
WDGL
t
HDGC
t
VDATDGH
t
DATRDGH
t
DGWRL
t
DGWRH
t
DGWRR
t
DGRDL
t
DRDGH
t
DGRDR
t
DGWR
t
DADGH
t
DDGHA
W = (number of wait states specified in WAIT register)
×
t
CKOP
.
HI = t
CKOP
(if data bus idle cycle occurs, as specified in WAIT register; otherwise HI = 0).
DMAGx
Low Delay After CLKIN
DMAGx
High Width
DMAGx
Low Width
DMAGx
High Delay After CLKIN
Data Valid Before
DMAGx
High
5
Data Disable After
DMAGx
High
6
WRx
Low Before
DMAGx
Low
DMAGx
Low Before
WRx
High
WRx
High Before
DMAGx
High
7
RDx
Low Before
DMAGx
Low
RDx
Low Before
DMAGx
High
RDx
High Before
DMAGx
High
7
DMAGx
High to
WRx
,
RDx
Low
Address/Select Valid to
DMAGx
High
Address/Select Hold After
DMAGx
High
0.25t
CCLK
+1
0.5t
CCLK
–1+HI
t
CKOP
–0.5t
CCLK
–1
t
CKOP
–0.25t
CCLK
+1.0
t
CKOP
–0.25t
CCLK
–8
0.25t
CCLK
–3
–1.5
t
CKOP
–0.5t
CCLK
–2+W
–1.5
–1.5
t
CKOP
–0.5t
CCLK
–2+W
–1.5
0.5t
CCLK
–2+HI
15
1
0.25t
CCLK
+9
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
t
CKOP
–0.25t
CCLK
+9
t
CKOP
–0.25t
CCLK
+5
0.25t
CCLK
+4
+2
+2
+2
+2
1
Only required for recognition in the current cycle.
2
Maximum throughput using
DMARx/DMAGx
handshaking equals t
WDR
+ t
DMARH
= (t
CCLK
+4.5) + (t
CCLK
+4.5)=29 ns (34.5 MHz). This throughput
limit applies to non-synchronous access mode only.
3
t
SDATDGL
is the data setup requirement if
DMARx
is not being used to hold off completion of a write. Otherwise, if
DMARx
low holds off completion of
the write, the data can be driven t
DATDRH
after
DMARx
is brought high.
4
Use t
DMARLL
if
DMARx
transitions synchronous with CLKIN. Otherwise, use t
WDR
and t
DMARH
.
5
t
VDATDGH
is valid if
DMARx
is not being used to hold off completion of a read. If
DMARx
is used to prolong the read, then
t
VDATDGH
= t
CKOP
– 0.25t
CCLK
– 8 + (n × t
CKOP
) where n equals the number of extra cycles that the access is prolonged.
6
See
Example System Hold Time Calculation on Page 51
for calculation of hold times given capacitive and dc loads.
7
This parameter applies for synchronous access mode only.
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ADSP-21161NKCA-100Z 制造商:Analog Devices 功能描述:
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