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參數(shù)資料
| 型號： | ADSP-21161NKCA-100 |
| 廠商： | ANALOG DEVICES INC |
| 元件分類： | 數(shù)字信號處理 |
| 英文描述： | DSP Microcomputer |
| 中文描述： | 48-BIT, 27.5 MHz, OTHER DSP, PBGA225 |
| 封裝： | 17 X 17 MM, MO-192AAF-2, BGA-225 |
| 文件頁數(shù)： | 23/60頁 |
| 文件大?。?/td> | 1019K |
| 代理商： | ADSP-21161NKCA-100 |
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–23–
REV. A
ADSP-21161N
Power-Up Sequencing – Silicon Revision 1.2
The timing requirements for DSP startup for silicon with revision
1.2 are given in
Table 9
.
RSTOUT
does not currently exist for ADSP-21161N revisions
0.3, 1.0, and 1.1. This new signal will be placed on one of the
current no-connect pins: ball B15.
During the power-up sequence of the DSP, differences in the
ramp-up rates and activation time between the two supplies can
cause current to flow in the I/O ESD protection circuitry. To
prevent damage to the ESD diode protection circuitry, Analog
Devices recommends including a bootstrap Schottky diode.
The bootstrap Schottky diode is connected between the 1.8 V
and 3.3 V power supplies as shown in
Figure 13
. It protects the
ADSP-21161N from partially powering the 3.3 V supply.
Including a Schottky diode will shorten the delay between
the supply ramps and thus prevent damage to the ESD diode
Table 9. Power-Up Sequencing for Revision 1.2 (DSP Startup)
Parameter
Timing Requirements
t
RSTVDD
t
IVDDEVDD
t
CLKVDD
t
CLKRST
t
PLLRST
t
WRST
Min
Max
Unit
RESET
Low Before V
DDINT
/V
DDEXT
on
V
DDINT
on Before V
DDEXT
CLKIN Valid After V
DDINT
/V
DDEXT
Valid
1
CLKIN Valid Before
RESET
Deasserted
2
PLL Control Setup Before
RESET
Deasserted
3
Subsequent
RESET
Low Pulsewidth
4
0
–50
0
10
20
4t
CK
ns
ms
ms
μs
μs
ns
+200
200
Switching Requirements
t
CORERST
DSP core reset deasserted after
RESET
deasserted
4080t
CK
3, 5
1
Valid V
DDINT
/V
DDEXT
assumes that the supplies are fully ramped to their 1.8 and 3.3 volt rails. Voltage ramp rates can vary from microseconds to hundreds
of milliseconds depending on the design of the power supply subsystem.
2
Assumes a stable CLKIN signal, after meeting worst-case start-up timing of crystal oscillators. Refer to the crystal oscillator manufacturer's data sheet for
start-up time. Assume a 25 ms maximum oscillator start-up time if using the XTAL pin and internal oscillator circuit in conjunction with an external crystal.
3
Based on CLKIN cycles
4
Applies after the power-up sequence is complete. Subsequent resets require a minimum of 4 CLKIN cycles for
RESET
to be held low in order to properly
initialize and propagate default states at all I/O pins.
5
The 4080 cycle count depends on t
SRST
specification in
Table 11
. If setup time is not met, one additional CLKIN cycle may be added to the core reset
time, resulting in 4081 cycles maximum.
Figure 12. Power-Up Sequencing for Revision 1.2 (DSP Startup)
RESET
RSTOUT
CLKDBL
CLK_CFG1-0
CLKIN
t
RSTVDD
VDDEXT
VDDINT
t
PLLRST
t
CLKRST
t
CLKVDD
t
IVDDEVDD
t
CORERST
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