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參數(shù)資料
| 型號： | ADSP-21065LKS-264 |
| 廠商： | ANALOG DEVICES INC |
| 元件分類： | 數(shù)字信號處理 |
| 英文描述： | DSP Microcomputer |
| 中文描述： | 32-BIT, 33.33 MHz, OTHER DSP, PQFP208 |
| 封裝： | MS-029FA-1, MQFP-208 |
| 文件頁數(shù)： | 8/44頁 |
| 文件大?。?/td> | 331K |
| 代理商： | ADSP-21065LKS-264 |
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REV. B
ADSP-21065L
–8–
Pin
Type
Function
HBR
I/A
Host Bus Request.
Must be asserted by a host processor to request control of the ADSP-
21065L’s external bus. When
HBR
is asserted in a multiprocessing system, the ADSP-21065L
that is bus master will relinquish the bus and assert
HBG
. To relinquish the bus, the ADSP-
21065L places the address, data, select, and strobe lines in a high impedance state. It does,
however, continue to drive the SDRAM control pins.
HBR
has priority over all ADSP-21065L
bus requests (
BR
2-1
) in a multiprocessor system.
Host Bus Grant
. Acknowledges an
HBR
bus request, indicating that the host processor may
take control of the external bus.
HBG
is asserted by the ADSP-21065L until
HBR
is released.
In a multiprocessor system,
HBG
is output by the ADSP-21065L bus master.
Chip Select.
Asserted by host processor to select the ADSP-21065L.
Host Bus Acknowledge.
The ADSP-21065L deasserts REDY to add wait states to an asyn-
chronous access of its internal memory or IOP registers by a host. Open drain output (O/D) by
default; can be programmed in ADREDY bit of SYSCON register to be active drive (A/D).
REDY will only be output if the
CS
and
HBR
inputs are asserted.
HBG
I/O
CS
REDY (O/D)
I/A
O
DMAR
1
I/A
DMA Request 1
(DMA Channel 9).
DMAR
2
I/A
DMA Request 2
(DMA Channel 8).
DMAG
1
O/T
DMA Grant 1
(DMA Channel 9).
DMAG
2
O/T
DMA Grant 2
(DMA Channel 8).
BR
2-1
I/O/S
Multiprocessing Bus Requests.
Used by multiprocessing ADSP-21065Ls to arbitrate for bus
mastership. An ADSP-21065L drives its own
BR
x line (corresponding to the value of its ID
2-0
inputs) only and monitors all others. In a uniprocessor system, tie both
BR
x pins to VDD.
ID
1-0
I
Multiprocessing ID.
Determines which multiprocessor bus request (
BR
1
–
BR
2
) is used by
ADSP-21065L. ID = 01 corresponds to
BR
1
, ID = 10 corresponds to
BR
2
. ID = 00 in single-
processor systems. These lines are a system configuration selection which should be hard-wired
or changed only at reset.
CPA
(O/D)
I/O
Core Priority Access.
Asserting its
CPA
pin allows the core processor of an ADSP-21065L
bus slave to interrupt background DMA transfers and gain access to the external bus.
CPA
is an
open drain output that is connected to both ADSP-21065Ls in the system. The
CPA
pin has an
internal 5 k
pull-up resistor. If core access priority is not required in a system, leave the
CPA
pin unconnected.
DTxX
O
Data Transmit
(Serial Ports 0, 1; Channels A, B). Each DTxX pin has a 50k
internal pull-
up resistor.
DRxX
I
Data Receive
(Serial Ports 0, 1; Channels A, B). Each DRxX pin has a 50 k
internal pull-up
resistor.
TCLKx
I/O
Transmit Clock
(Serial Ports 0, 1). Each TCLK pin has a 50 k
internal pull-up resistor.
RCLKx
I/O
Receive Clock
(Serial Ports 0, 1). Each RCLK pin has a 50 k
internal pull-up resistor.
TFSx
I/O
Transmit Frame Sync
(Serial Ports 0, 1).
RFSx
I/O
Receive Frame Sync
(Serial Ports 0, 1).
BSEL
I
EPROM Boot Select.
When BSEL is high, the ADSP-21065L is configured for booting from
an 8-bit EPROM. When BSEL is low, the BSEL and
BMS
inputs determine booting mode. See
BMS
for details. This signal is a system configuration selection which should be hard-wired.
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| ADSP-21065LKSZ-240 | 功能描述:IC DSP CONTROLLR 544KBIT 208MQFP RoHS:是 類別:集成電路 (IC) >> 嵌入式 - DSP（數(shù)字式信號處理器） 系列:SHARC® 標(biāo)準(zhǔn)包裝:40 系列:TMS320DM64x, DaVinci™ 類型:定點(diǎn) 接口:I²C，McASP，McBSP 時(shí)鐘速率:400MHz 非易失內(nèi)存:外部 芯片上RAM:160kB 電壓 - 輸入/輸出:3.30V 電壓 - 核心:1.20V 工作溫度:0°C ~ 90°C 安裝類型:表面貼裝 封裝/外殼:548-BBGA，F(xiàn)CBGA 供應(yīng)商設(shè)備封裝:548-FCBGA（27x27） 包裝:托盤 配用:TMDSDMK642-0E-ND - DEVELPER KIT W/NTSC CAMERA296-23038-ND - DSP STARTER KIT FOR TMS320C6416296-23059-ND - FLASHBURN PORTING KIT296-23058-ND - EVAL MODULE FOR DM642TMDSDMK642-ND - DEVELOPER KIT W/NTSC CAMERA |
| ADSP-21065LKSZ-264 | 功能描述:IC DSP CONTROLL 544KBIT 208-MQFP RoHS:是 類別:集成電路 (IC) >> 嵌入式 - DSP（數(shù)字式信號處理器） 系列:SHARC® 標(biāo)準(zhǔn)包裝:40 系列:TMS320DM64x, DaVinci™ 類型:定點(diǎn) 接口:I²C，McASP，McBSP 時(shí)鐘速率:400MHz 非易失內(nèi)存:外部 芯片上RAM:160kB 電壓 - 輸入/輸出:3.30V 電壓 - 核心:1.20V 工作溫度:0°C ~ 90°C 安裝類型:表面貼裝 封裝/外殼:548-BBGA，F(xiàn)CBGA 供應(yīng)商設(shè)備封裝:548-FCBGA（27x27） 包裝:托盤 配用:TMDSDMK642-0E-ND - DEVELPER KIT W/NTSC CAMERA296-23038-ND - DSP STARTER KIT FOR TMS320C6416296-23059-ND - FLASHBURN PORTING KIT296-23058-ND - EVAL MODULE FOR DM642TMDSDMK642-ND - DEVELOPER KIT W/NTSC CAMERA |
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