參數(shù)資料
型號： ADSP-21065LKS-264
廠商： ANALOG DEVICES INC
元件分類： 數(shù)字信號處理
英文描述： DSP Microcomputer
中文描述： 32-BIT, 33.33 MHz, OTHER DSP, PQFP208
封裝： MS-029FA-1, MQFP-208
文件頁數(shù)： 20/44頁
文件大?。?/td> 331K
代理商： ADSP-21065LKS-264
REV. B
ADSP-21065L
–20–
Synchronous Read/Write—Bus Slave
Use these specifications for ADSP-21065L bus master accesses of a slave’s IOP registers or internal memory (in multiprocessor
memory space). The bus master must meet these (bus slave) timing requirements.
Parameter
Min
Max
Units
Timing Requirements:
t
SADRI
t
HADRI
t
SRWLI
t
HRWLI
t
RWHPI
t
SDATWH
t
HDATWH
Address,
SW
Setup Before CLKIN
Address,
SW
Hold Before CLKIN
RD
/
WR
Low Setup Before CLKIN
1
RD
/
WR
Low Hold After CLKIN
RD
/
WR
Pulse High
Data Setup Before
WR
High
Data Hold After
WR
High
24.5 + 25 DT
ns
ns
ns
ns
ns
ns
ns
4.0 + 8 DT
21.0 + 21 DT
–2.50 – 5 DT
2.5
4.5
0.0
7.5 + 7 DT
Switching Characteristics:
t
SDDATO
t
DATTR
t
DACK
t
ACKTR
Data Delay After CLKIN
Data Disable After CLKIN
2
ACK Delay After CLKIN
ACK Disable After CLKIN
2
31.75 + 21 DT
7.0 – 2 DT
29.5 + 20 DT
6.0 – 2 DT
ns
ns
ns
ns
1.0 – 2 DT
1.0 – 2 DT
NOTES
1
t
is specified when Multiprocessor Memory Space Wait State (MMSWS bit in WAIT register) is disabled; when MMSWS is enabled, t
SRWLI
(min) = 17.5 + 18 DT.
2
See System Hold Time Calculation under Test Conditions for calculation of hold times given capacitive and dc loads.
For two ADSP-21065Ls to communicate synchronously as master and slave, certain master and slave specification combinations
must be satisfied. Do not compare specification values directly to calculate master/slave clock skew margins for those specifications
listed below. The following table shows the appropriate clock skew margin.
Table IV. Bus Master to Slave Skew Margins
Master Specification
Slave Specification
Skew Margin
t
SSDATI
t
SDDATO
t
CK
= 33.3 ns + 2.25 ns
t
CK
= 30.0 ns
t
CK
= 33.3 ns
t
CK
= 30.0 ns
t
CK
= 33.3 ns
t
CK
= 30.0 ns
t
CK
= 33.3 ns
t
CK
= 30.0 ns
t
CK
= 33.3 ns
t
CK
= 30.0 ns
t
CK
= 33.3 ns
t
CK
= 30.0 ns
+ 1.50 ns
+ 3.00 ns
+ 2.25 ns
N/A
+ 2.75 ns
+ 1.50 ns
+ 1.25 ns
N/A
3.00 ns
N/A
3.75 ns
t
SACKC
t
DACK
t
DADRO
t
SADRI
t
DRWL
(Max)
t
SRWLI
t
DRDO
(Max)
t
HRWLI
(Max)
t
DWRO
(Max)
t
HRWLI
(Max)
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