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參數(shù)資料
| 型號(hào)： | ADSP-21065LKS-264 |
| 廠商： | ANALOG DEVICES INC |
| 元件分類： | 數(shù)字信號(hào)處理 |
| 英文描述： | DSP Microcomputer |
| 中文描述： | 32-BIT, 33.33 MHz, OTHER DSP, PQFP208 |
| 封裝： | MS-029FA-1, MQFP-208 |
| 文件頁(yè)數(shù)： | 36/44頁(yè) |
| 文件大小： | 331K |
| 代理商： | ADSP-21065LKS-264 |
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REV. B
ADSP-21065L
–36–
OUTPUT DRIVE CURRENT
SOURCE VOLTAGE
–
V
80
0
3.50
S
–
0.50
1.00
1.50
2.00
2.50
3.00
60
–
40
–
100
–
120
20
–
20
40
0
–
80
–
60
3.3V, +25 C
3.6V,
–
40 C
3.1V, +100 C
3.6V,
–
40 C
V
OL
V
OH
3.1V, +85 C
3.1V, +100 C
3.1V, +85 C
3.3V, +25 C
Figure 24. Typical Drive Currents
TEST CONDITIONS
Output Disable Time
Output pins are considered to be disabled when they stop driv-
ing, go into a high impedance state, and start to decay from
their output high or low voltage. The time for the voltage on the
bus to decay by
V is dependent on the capacitive load, C
L
and
the load current, I
L
. This decay time can be approximated by
the following equation:
t
C
V
I
DECAY
L
L
=
×
The output disable time t
DIS
is the difference between t
MEASURED
and t
DECAY
as shown in Figure 26. The time t
MEASURED
is the
interval from when the reference signal switches to when the
output voltage decays
V from the measured output high or
output low voltage. t
DECAY
is calculated with test loads C
L
and
I
L
, and with
V equal to 0.5 V.
Output Enable Time
Output pins are considered to be enabled when they have made
a transition from a high impedance state to when they start
driving. The output enable time t
ENA
is the interval from when a
reference signal reaches a high or low voltage level to when the
output has reached a specified high or low trip point, as shown
in the Output Enable/Disable diagram. If multiple pins (such as
the data bus) are enabled, the measurement value is that of the
first pin to start driving.
Example System Hold Time Calculation
To determine the data output hold time in a particular system,
first calculate t
DECAY
using the equation given above. Choose
V
to be the difference between the ADSP-21065L’s output voltage
and the input threshold for the device requiring the hold time. A
typical
V will be 0.4 V. C
L
is the total bus capacitance (per
data line), and I
L
is the total leakage or three-state current (per
data line). The hold time will be t
DECAY
plus the minimum
disable time (i.e., t
DATRWH
for the write cycle).
REFERENCE
SIGNAL
t
DIS
OUTPUT STARTS
DRIVING
V
OH (MEASURED)
–
V
V
OL (MEASURED)
+ V
t
DECAY
t
MEASURED
V
OH (MEASURED)
V
OL (MEASURED)
2.0V
1.0V
V
OH (MEASURED)
V
OL (MEASURED)
HIGH-IMPEDANCE STATE.
TEST CONDITIONS CAUSE
THIS VOLTAGE TO BE
APPROXIMATELY 1.5V
OUTPUT STOPS
DRIVING
t
ENA
OUTPUT
Figure 25. Output Enable
+1.5V
50pF
TO
OUTPUT
PIN
I
OL
I
OH
Figure 26. Equivalent Device Loading for AC Measure-
ments (Includes All Fixtures)
INPUT OR
OUTPUT
1.5V
1.5V
Figure 27. Voltage Reference Levels for AC Measure-
ments (Except Output Enable/Disable)
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參數(shù)描述 |
|---|---|
| ADSP-21065LKSZ-240 | 功能描述:IC DSP CONTROLLR 544KBIT 208MQFP RoHS:是 類別:集成電路 (IC) >> 嵌入式 - DSP（數(shù)字式信號(hào)處理器） 系列:SHARC® 標(biāo)準(zhǔn)包裝:40 系列:TMS320DM64x, DaVinci™ 類型:定點(diǎn) 接口:I²C，McASP，McBSP 時(shí)鐘速率:400MHz 非易失內(nèi)存:外部 芯片上RAM:160kB 電壓 - 輸入/輸出:3.30V 電壓 - 核心:1.20V 工作溫度:0°C ~ 90°C 安裝類型:表面貼裝 封裝/外殼:548-BBGA，F(xiàn)CBGA 供應(yīng)商設(shè)備封裝:548-FCBGA（27x27） 包裝:托盤 配用:TMDSDMK642-0E-ND - DEVELPER KIT W/NTSC CAMERA296-23038-ND - DSP STARTER KIT FOR TMS320C6416296-23059-ND - FLASHBURN PORTING KIT296-23058-ND - EVAL MODULE FOR DM642TMDSDMK642-ND - DEVELOPER KIT W/NTSC CAMERA |
| ADSP-21065LKSZ-264 | 功能描述:IC DSP CONTROLL 544KBIT 208-MQFP RoHS:是 類別:集成電路 (IC) >> 嵌入式 - DSP（數(shù)字式信號(hào)處理器） 系列:SHARC® 標(biāo)準(zhǔn)包裝:40 系列:TMS320DM64x, DaVinci™ 類型:定點(diǎn) 接口:I²C，McASP，McBSP 時(shí)鐘速率:400MHz 非易失內(nèi)存:外部 芯片上RAM:160kB 電壓 - 輸入/輸出:3.30V 電壓 - 核心:1.20V 工作溫度:0°C ~ 90°C 安裝類型:表面貼裝 封裝/外殼:548-BBGA，F(xiàn)CBGA 供應(yīng)商設(shè)備封裝:548-FCBGA（27x27） 包裝:托盤 配用:TMDSDMK642-0E-ND - DEVELPER KIT W/NTSC CAMERA296-23038-ND - DSP STARTER KIT FOR TMS320C6416296-23059-ND - FLASHBURN PORTING KIT296-23058-ND - EVAL MODULE FOR DM642TMDSDMK642-ND - DEVELOPER KIT W/NTSC CAMERA |
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