參數(shù)資料
型號: ADSP-21061LKB-160
廠商: ANALOG DEVICES INC
元件分類: 數(shù)字信號處理
英文描述: ADSP-2106x SHARC DSP Microcomputer Family
中文描述: 48-BIT, 40 MHz, OTHER DSP, PBGA225
封裝: PLASTIC, BGA-225
文件頁數(shù): 41/47頁
文件大?。?/td> 367K
代理商: ADSP-21061LKB-160
ADSP-21061/ADSP-21061L
–41–
REV. B
ENVIRONMENTAL CONDITIONS
Thermal Characteristics
The ADSP-21061KS (5 V) device is packaged in a 240-lead
thermally enhanced MQFP. The top surface of the package
contains a copper slug from which most of the die heat is dissi-
pated. The slug is flush with the top surface of the package.
Note that the copper slug is internally connected to GND
through the device substrate. The ADSP-21061LKS is packaged
in a 240-lead MQFP without a copper heat slug. The ADSP-
21061L is also available in a 225-Ball PBGA package. The
PBGA has a
θ
JC
of 1.7
°
C/W. The ADSP-2106x is specified for a
case temperature (T
CASE
). To ensure that the T
CASE
data sheet
specification is not exceeded, a heatsink and/or an air flow
source may be used. A heatsink should be attached with a ther-
mal adhesive.
T
CASE
=
T
AMB
+
(
PD
× θ
CA
)
T
CASE
= Case temperature (measured on top surface of package)
PD
=
Power dissipation in W (this value depends upon the
specific application; a method for calculating
PD
is
shown under Power Dissipation).
θ
CA
=
Value from tables below.
ADSP-21061 (5 V MQFP Package)
JC
= 0.3 C/W
Airflow
(Linear Ft./Min.)
θ
CA
(
°
C/W)
0
100
200
400
600
10
9
8
7
6
NOTES
This represents thermal resistance at total power of 5 W.
With air flow, no variance is seen in
θ
CA
with power.
θ
CA
at 0 LFM varies with power: at 2W,
θ
CA
= 14
°
C/W, at 3W
θ
CA
= 11
°
C/W.
ADSP-21061L (3.3 V MQFP Package)
JC
= 6.3 C/W
Airflow
(Linear Ft./Min.)
θ
CA
(
°
C/W)
0
100
200
400
600
19.6
17.6
15.6
13.9
12.2
NOTE
With air flow, no variance is seen in
θ
CA
with power.
ADSP-21061L (3.3 V PBGA Package)
JC
= 1.7 C/W
Airflow
(Linear Ft./Min.)
θ
CA
(
°
C/W)
0
200
400
19.0
13.6
11.2
NOTE
With air flow, no variance is seen in
θ
CA
with power.
LOAD CAPACITANCE
pF
0
0
20
40
60
80
100
120
Y = 0.0391X + 0.36
Y = 0.0305X + 0.24
RISE TIME
FALL TIME
140
160
180
200
R
1
2
3
4
5
6
7
8
9
Figure 33. Typical Output Rise Time (0.8 V–2.0 V) vs.
Load Capacitance (V
DD
= 3.3 V)
LOAD CAPACITANCE
pF
O
5
1
25
200
50
75
100
125
150
175
4
3
2
1
NOMINAL
Y = 0.0329X
1.65
Figure 34. Typical Output Delay or Hold vs. Load Capaci-
tance (at Maximum Case Temperature) (V
DD
= 3.3 V)
相關(guān)PDF資料
PDF描述
ADSP-21061LKB-176 ADSP-2106x SHARC DSP Microcomputer Family
ADSP-21061LKS-160 ADSP-2106x SHARC DSP Microcomputer Family
ADSP-21061LKS-176 ADSP-2106x SHARC DSP Microcomputer Family
ADSP-21062CS-160 ADSP-2106x SHARC DSP Microcomputer Family
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