參數(shù)資料
型號： ADSP-21061LKB-160
廠商： ANALOG DEVICES INC
元件分類： 數(shù)字信號處理
英文描述： ADSP-2106x SHARC DSP Microcomputer Family
中文描述： 48-BIT, 40 MHz, OTHER DSP, PBGA225
封裝： PLASTIC, BGA-225
文件頁數(shù)： 11/47頁
文件大?。?/td> 367K
代理商： ADSP-21061LKB-160
ADSP-21061/ADSP-21061L
–11–
REV. B
Pin
Type
Function
TFSx
RFSx
EBOOT
I/O
I/O
I
Transmit Frame Sync
(Serial Ports 0, 1).
Receive Frame Sync
(Serial Ports 0, 1).
EPROM Boot Select
. When EBOOT is high, the ADSP-21061 is configured for booting from an 8-
bit EPROM. When EBOOT is low, the LBOOT and
BMS
inputs determine booting mode. See table
below. This signal is a system configuration selection which should be hardwired.
Link Boot—Must be tied to GND.
Boot Memory Select
.
Output
: Used as chip select for boot EPROM devices (when EBOOT = 1,
LBOOT = 0). In a multiprocessor system,
BMS
is output by the bus master.
Input:
When low, indi-
cates that no booting will occur and that ADSP-21061 will begin executing instructions from external
memory. See table below. This input is a system configuration selection which should be hardwired.
*Three-statable only in EPROM boot mode (when
BMS
is an output).
EBOOT
LBOOT
BMS
Booting Mode
1
0
Output
EPROM (Connect
BMS
to EPROM chip select.)
0
0
1 (Input)
Host Processor
0
0
0 (Input)
No Booting. Processor executes from external memory.
LBOOT
BMS
I
I/O/T*
CLKIN
I
Clock In
. External clock input to the ADSP-21061. The instruction cycle rate is equal to CLKIN.
CLKIN may not be halted, changed, or operated below the specified frequency.
Processor Reset
. Resets the ADSP-21061 to a known state and begins execution at the program
memory location specified by the hardware reset vector address. This input must be asserted (low) at
power-up.
Test Clock (JTAG)
. Provides an asynchronous clock for JTAG boundary scan.
Test Mode Select (JTAG)
. Used to control the test state machine. TMS has a 20 k
internal pull-up
resistor.
Test Data Input (JTAG)
. Provides serial data for the boundary scan logic. TDI has a 20 k
internal
pull-up resistor.
Test Data Output (JTAG)
. Serial scan output of the boundary scan path.
Test Reset (JTAG)
. Resets the test state machine.
TRST
must be asserted (pulsed low) after power-
up or held low for proper operation of the ADSP-21061.
TRST
has a 20 k
internal pull-up resistor.
Emulation Status
. Must be connected to the ADSP-21061 EZ-ICE
target board connector
only
.
Reserved
, leave unconnected.
Power Supply
; nominally +3.3 V dc for ADSP-21061L, +5.0 V dc for ADSP-21061.
Power Supply Return
.
Do Not Connect
. Reserved pins which must be left open and unconnected.
RESET
I/A
TCK
TMS
I
I/S
TDI
I/S
TDO
TRST
O
I/A
EMU
ICSA
VDD
GND
NC
O
O
P
G
相關(guān)PDF資料
PDF描述
ADSP-21061LKB-176 ADSP-2106x SHARC DSP Microcomputer Family
ADSP-21061LKS-160 ADSP-2106x SHARC DSP Microcomputer Family
ADSP-21061LKS-176 ADSP-2106x SHARC DSP Microcomputer Family
ADSP-21062CS-160 ADSP-2106x SHARC DSP Microcomputer Family
ADSP-21062KS-133 ADSP-2106x SHARC DSP Microcomputer Family
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
ADSP-21061LKB-176 制造商:AD 制造商全稱:Analog Devices 功能描述:DSP Microcomputer Family
ADSP-21061LKBZ-160 功能描述:IC DSP CONTROLLER 32BIT 225-BGA RoHS:是 類別:集成電路 (IC) >> 嵌入式 - DSP（數(shù)字式信號處理器） 系列:SHARC® 標(biāo)準(zhǔn)包裝:2 系列:StarCore 類型:SC140 內(nèi)核 接口:DSI，以太網(wǎng)，RS-232 時鐘速率:400MHz 非易失內(nèi)存:外部 芯片上RAM:1.436MB 電壓 - 輸入/輸出:3.30V 電壓 - 核心:1.20V 工作溫度:-40°C ~ 105°C 安裝類型:表面貼裝 封裝/外殼:431-BFBGA，F(xiàn)CBGA 供應(yīng)商設(shè)備封裝:431-FCPBGA（20x20） 包裝:托盤
ADSP21061LKS160 制造商:Analog Devices 功能描述:DSP Floating-Point 32-Bit 40MHz 40MIPS 240-Pin MQFP Tray
ADSP-21061LKS-160 制造商:Rochester Electronics LLC 功能描述:ADSP-21061 1MBIT,40MHZ, 3V SHARC - Bulk 制造商:Analog Devices 功能描述:IC SHARC DSP 40MHZ 21061 MQFP240
ADSP-21061LKS-176 制造商:Analog Devices 功能描述:DSP Floating-Point 32-Bit 44MHz 44MIPS 240-Pin MQFP Tray 制造商:Rochester Electronics LLC 功能描述:ADSP-21061L 44HZ, 3V SHARC - Bulk
發(fā)布緊急采購，3分鐘左右您將得到回復(fù)。

采購需求

(若只采購一條型號，填寫一行即可)

發(fā)布成功！您可以繼續(xù)發(fā)布采購。也可以進(jìn)入我的后臺，查看報價

發(fā)布成功！您可以繼續(xù)發(fā)布采購。也可以進(jìn)入我的后臺，查看報價

*型號 *數(shù)量 廠商 批號 封裝
添加更多采購

我的聯(lián)系方式

*
*
*