參數(shù)資料
型號(hào)： ADSP-21061LKB-160
廠(chǎng)商： ANALOG DEVICES INC
元件分類(lèi)： 數(shù)字信號(hào)處理
英文描述： ADSP-2106x SHARC DSP Microcomputer Family
中文描述： 48-BIT, 40 MHz, OTHER DSP, PBGA225
封裝： PLASTIC, BGA-225
文件頁(yè)數(shù)： 26/47頁(yè)
文件大?。?/td> 367K
代理商： ADSP-21061LKB-160
–26–
ADSP-21061/ADSP-21061L
REV. B
ADSP-21061 (5 V)
Min
ADSP-21061L (3.3 V)
Min
Parameter
Max
Max
Unit
Timing Requirements:
t
HBGRCSV
t
SHBRI
t
HHBRI
t
SHBGI
t
HHBGI
t
SBRI
t
HBRI
t
SRPBAI
t
HRPBAI
HBG
Low to
RD
/
WR
/
CS
Valid
1
HBR
Setup before CLKIN
2
HBR
Hold before CLKIN
2
HBG
Setup before CLKIN
HBG
Hold before CLKIN High
BR
x,
CPA
Setup before CLKIN
3
BR
x,
CPA
Hold before CLKIN High
RPBA Setup before CLKIN
RPBA Hold before CLKIN
20+ 5DT/4
20 + 5DT/4
ns
ns
ns
ns
ns
ns
ns
ns
ns
20 + 3DT/4
20 + 3DT/4
14 + 3DT/4
14 + 3DT/4
13 + DT/2
13 + DT/2
6 + DT/2
6 + DT/2
13 + DT/2
13 + DT/2
6 + DT/2
6 + DT/2
20 + 3DT/4
20 + 3DT/4
12 + 3DT/4
12 + 3DT/4
Switching Characteristics:
t
DHBGO
t
HHBGO
t
DBRO
t
HBRO
t
DCPAO
t
TRCPA
t
DRDYCS
HBG
Delay after CLKIN
HBG
Hold after CLKIN
BR
x Delay after CLKIN
BR
x Hold after CLKIN
CPA
Low Delay after CLKIN
CPA
Disable after CLKIN
REDY (O/D) or (A/D) Low from
CS
and
HBR
Low
4
REDY (O/D) Disable or REDY (A/D)
High from
HBG
4
REDY (A/D) Disable from
CS
or
HBR
High
4
7 – DT/8
7 – DT/8
ns
ns
ns
ns
ns
ns
–2 – DT/8
–2 – DT/8
5.5 – DT/8
5.5 – DT/8
–2 – DT/8
–2 – DT/8
6.5 – DT/8
4.5 – DT/8
8.5 – DT/8
4.5 – DT/8
–2 – DT/8
–2 – DT/8
8
12
ns
t
TRDYHG
44 + 27DT/16
40 + 27DT/16
ns
t
ARDYTR
10
10
ns
NOTES
1
For first asynchronous access after
HBR
and
CS
asserted, ADDR
31-0
must be a non-MMS value 1/2 t
CK
before
RD
or
WR
goes low or by t
HBGRCSV
after HBG goes
low. This is easily accomplished by driving an upper address signal high when
HBG
is asserted. See the Host Processor Control of the ADSP-2106x section in the
ADSP-2106x SHARC User’s Manual, Second Edition.
2
Only required for recognition in the current cycle.
3
CPA
assertion must meet the setup to CLKIN; deassertion does not need to meet the setup to CLKIN.
4
(O/D) = open drain, (A/D) = active drive.
Multiprocessor Bus Request and Host Bus Request
Use these specifications for passing of bus mastership between
multiprocessing ADSP-21061s (
BR
x) or a host processor
(
HBR
,
HBG
).
相關(guān)PDF資料
PDF描述
ADSP-21061LKB-176 ADSP-2106x SHARC DSP Microcomputer Family
ADSP-21061LKS-160 ADSP-2106x SHARC DSP Microcomputer Family
ADSP-21061LKS-176 ADSP-2106x SHARC DSP Microcomputer Family
ADSP-21062CS-160 ADSP-2106x SHARC DSP Microcomputer Family
ADSP-21062KS-133 ADSP-2106x SHARC DSP Microcomputer Family
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
ADSP-21061LKB-176 制造商:AD 制造商全稱(chēng):Analog Devices 功能描述:DSP Microcomputer Family
ADSP-21061LKBZ-160 功能描述:IC DSP CONTROLLER 32BIT 225-BGA RoHS:是 類(lèi)別:集成電路 (IC) >> 嵌入式 - DSP（數(shù)字式信號(hào)處理器） 系列:SHARC® 標(biāo)準(zhǔn)包裝:2 系列:StarCore 類(lèi)型:SC140 內(nèi)核 接口:DSI，以太網(wǎng)，RS-232 時(shí)鐘速率:400MHz 非易失內(nèi)存:外部 芯片上RAM:1.436MB 電壓 - 輸入/輸出:3.30V 電壓 - 核心:1.20V 工作溫度:-40°C ~ 105°C 安裝類(lèi)型:表面貼裝 封裝/外殼:431-BFBGA，F(xiàn)CBGA 供應(yīng)商設(shè)備封裝:431-FCPBGA（20x20） 包裝:托盤(pán)
ADSP21061LKS160 制造商:Analog Devices 功能描述:DSP Floating-Point 32-Bit 40MHz 40MIPS 240-Pin MQFP Tray
ADSP-21061LKS-160 制造商:Rochester Electronics LLC 功能描述:ADSP-21061 1MBIT,40MHZ, 3V SHARC - Bulk 制造商:Analog Devices 功能描述:IC SHARC DSP 40MHZ 21061 MQFP240
ADSP-21061LKS-176 制造商:Analog Devices 功能描述:DSP Floating-Point 32-Bit 44MHz 44MIPS 240-Pin MQFP Tray 制造商:Rochester Electronics LLC 功能描述:ADSP-21061L 44HZ, 3V SHARC - Bulk
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