參數(shù)資料
型號(hào)： ADSP-21060LKB-160
廠商： ANALOG DEVICES INC
元件分類： 數(shù)字信號(hào)處理
英文描述： RES, 2.2 K SM CHIP 5% 50V 1/16 WATT, 0603
中文描述： 48-BIT, 40 MHz, OTHER DSP, PBGA225
封裝： PLASTIC, MS-034AAJ-2, BGA-225
文件頁(yè)數(shù)： 8/47頁(yè)
文件大?。?/td> 366K
代理商： ADSP-21060LKB-160
–8–
ADSP-21060/ADSP-21060L
REV. D
Pin
Type
Function
ADDR
31-0
I/O/T
External Bus Address
. The ADSP-2106x outputs addresses for external memory and peripherals on
these pins. In a multiprocessor system the bus master outputs addresses for read/writes of the internal
memory or IOP registers of other ADSP-2106xs. The ADSP-2106x inputs addresses when a host
processor or multiprocessing bus master is reading or writing its internal memory or IOP registers.
External Bus Data
. The ADSP-2106x inputs and outputs data and instructions on these pins. 32-bit
single-precision floating-point data and 32-bit fixed-point data is transferred over bits 47–16 of the
bus. 40-bit extended-precision floating-point data is transferred over bits 47–8 of the bus. 16-bit short
word data is transferred over bits 31–16 of the bus. In PROM boot mode, 8-bit data is transferred over
bits 23–16. Pull-up resistors on unused DATA pins are not necessary.
Memory Select Lines
. These lines are asserted (low) as chip selects for the corresponding banks of
external memory. Memory bank size must be defined in the ADSP-2106x’s system control register
(SYSCON). The
MS
3-0
lines are decoded memory address lines that change at the same time as the
other address lines. When no external memory access is occurring the
MS
3-0
lines are inactive; they are
active however when a conditional memory access instruction is executed, whether or not the condition
is true.
MS
0
can be used with the PAGE signal to implement a bank of DRAM memory (Bank 0). In a
multiprocessing system the
MS
3-0
lines are output by the bus master.
Memory Read Strobe
. This pin is asserted (low) when the ADSP-2106x reads from external memory
devices or from the internal memory of other ADSP-2106xs. External devices (including other ADSP-
2106xs) must assert
RD
to read from the ADSP-2106x’s internal memory. In a multiprocessing system
RD
is output by the bus master and is input by all other ADSP-2106xs.
Memory Write Strobe
. This pin is asserted (low) when the ADSP-2106x writes to external memory
devices or to the internal memory of other ADSP-2106xs. External devices must assert
WR
to write to
the ADSP-2106x’s internal memory. In a multiprocessing system
WR
is output by the bus master and
is input by all other ADSP-2106xs.
DRAM Page Boundary
. The ADSP-2106x asserts this pin to signal that an external DRAM page
boundary has been crossed. DRAM page size must be defined in the ADSP-2106x’s memory control
register (WAIT). DRAM can only be implemented in external memory Bank 0; the PAGE signal can
only be activated for Bank 0 accesses. In a multiprocessing system PAGE is output by the bus master.
Clock Output Reference
. In a multiprocessing system ADRCLK is output by the bus master.
Synchronous Write Select
. This signal is used to interface the ADSP-2106x to synchronous
memory devices (including other ADSP-2106xs). The ADSP-2106x asserts
SW
(low) to provide an
early indication of an impending write cycle, which can be aborted if
WR
is not later asserted (e.g., in a
conditional write instruction). In a multiprocessing system,
SW
is output by the bus master and is
input by all other ADSP-2106xs to determine if the multiprocessor memory access is a read or write.
SW
is asserted at the same time as the address output. A host processor using synchronous writes must
assert this pin when writing to the ADSP-2106x(s).
Memory Acknowledge
. External devices can deassert ACK (low) to add wait states to an external
memory access. ACK is used by I/O devices, memory controllers, or other peripherals to hold off
completion of an external memory access. The ADSP-2106x deasserts ACK as an output to add wait
states to a synchronous access of its internal memory. In a multiprocessing system, a slave ADSP-
2106x deasserts the bus master’s ACK input to add wait state(s) to an access of its internal memory.
The bus master has a keeper latch on its ACK pin that maintains the input at the level it was last
driven to.
DATA
47-0
I/O/T
MS
3-0
O/T
RD
I/O/T
WR
I/O/T
PAGE
O/T
ADRCLK
SW
O/T
I/O/T
ACK
I/O/S
PIN FUNCTION DESCRIPTIONS
ADSP-21060 pin definitions are listed below. All pins are iden-
tical on the ADSP-21060 and ADSP-21060L. Inputs identified
as synchronous (S) must meet timing requirements with respect
to CLKIN (or with respect to TCK for TMS, TDI). Inputs
identified as asynchronous (A) can be asserted asynchronously
to CLKIN (or to TCK for
TRST
).
Unused inputs should be tied or pulled to VDD or GND,
except for ADDR
31-0
, DATA
47-0
, FLAG
3-0
,
SW
, and inputs that
have internal pull-up or pull-down resistors (
CPA
, ACK, DTx,
DRx, TCLKx, RCLKx, LxDAT
3-0
, LxCLK, LxACK, TMS and
TDI)—these pins can be left floating. These pins have a logic-
level hold circuit that prevents the input from floating
internally.
A = Asynchronous
G = Ground
O = Output
P = Power Supply
(A/D) = Active Drive
(O/D) = Open Drain
T = Three-State (when
SBTS
is asserted, or when the
ADSP-2106x is a bus slave)
I = Input
S = Synchronous
相關(guān)PDF資料
PDF描述
ADSP-21060LKS-133 ADSP-2106x SHARC DSP Microcomputer Family
ADSP-21060LKS-160 ADSP-2106x SHARC DSP Microcomputer Family
ADSP-21061KS-133 ADSP-2106x SHARC DSP Microcomputer Family
ADSP-21061 ADSP-2106x SHARC DSP Microcomputer Family
ADSP-21061L ADSP-2106x SHARC DSP Microcomputer Family
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
ADSP-21060LKBZ-160 制造商:Rochester Electronics LLC 功能描述: 制造商:Analog Devices 功能描述:
ADSP-21060LKS-133 制造商:Analog Devices 功能描述:DSP Floating-Point 32-Bit 33MHz 33MIPS 240-Pin MQFP 制造商:Rochester Electronics LLC 功能描述:FLOATING PT PROCESSOR, 3.3V, 33MHZ. - Bulk
ADSP-21060LKS-160 功能描述:IC DSP CONTROLLER 32BIT 240MQFP RoHS:否 類別:集成電路 (IC) >> 嵌入式 - DSP（數(shù)字式信號(hào)處理器） 系列:SHARC® 標(biāo)準(zhǔn)包裝:2 系列:StarCore 類型:SC140 內(nèi)核 接口:DSI，以太網(wǎng)，RS-232 時(shí)鐘速率:400MHz 非易失內(nèi)存:外部 芯片上RAM:1.436MB 電壓 - 輸入/輸出:3.30V 電壓 - 核心:1.20V 工作溫度:-40°C ~ 105°C 安裝類型:表面貼裝 封裝/外殼:431-BFBGA，F(xiàn)CBGA 供應(yīng)商設(shè)備封裝:431-FCPBGA（20x20） 包裝:托盤(pán)
ADSP-21060LKSZ-133 功能描述:IC DSP CONTROLLER 32BIT 240-MQFP RoHS:是 類別:集成電路 (IC) >> 嵌入式 - DSP（數(shù)字式信號(hào)處理器） 系列:SHARC® 標(biāo)準(zhǔn)包裝:2 系列:StarCore 類型:SC140 內(nèi)核 接口:DSI，以太網(wǎng)，RS-232 時(shí)鐘速率:400MHz 非易失內(nèi)存:外部 芯片上RAM:1.436MB 電壓 - 輸入/輸出:3.30V 電壓 - 核心:1.20V 工作溫度:-40°C ~ 105°C 安裝類型:表面貼裝 封裝/外殼:431-BFBGA，F(xiàn)CBGA 供應(yīng)商設(shè)備封裝:431-FCPBGA（20x20） 包裝:托盤(pán)
ADSP-21060LKSZ-160 功能描述:IC DSP CONTROLLER 32BIT 240MQFP RoHS:是 類別:集成電路 (IC) >> 嵌入式 - DSP（數(shù)字式信號(hào)處理器） 系列:SHARC® 標(biāo)準(zhǔn)包裝:2 系列:StarCore 類型:SC140 內(nèi)核 接口:DSI，以太網(wǎng)，RS-232 時(shí)鐘速率:400MHz 非易失內(nèi)存:外部 芯片上RAM:1.436MB 電壓 - 輸入/輸出:3.30V 電壓 - 核心:1.20V 工作溫度:-40°C ~ 105°C 安裝類型:表面貼裝 封裝/外殼:431-BFBGA，F(xiàn)CBGA 供應(yīng)商設(shè)備封裝:431-FCPBGA（20x20） 包裝:托盤(pán)
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