參數(shù)資料
型號: ADSP-1981BL
廠商: Analog Devices, Inc.
元件分類: Codec
英文描述: AC 97 SoundMAX Codec
中文描述: 交流97 SoundMAX編解碼器
文件頁數(shù): 22/32頁
文件大?。?/td> 326K
代理商: ADSP-1981BL
AD1981BL
EXTENDED AUDIO ID REGISTER
Index 0x28
Rev. A | Page 22 of 32
Reg No.
0x28
The extended audio ID register identifies which extended audio features are supported. A nonzero extended audio ID value indicates that one or more of the
extended audio features are supported.
All registers are not shown, and bits containing an X are assumed to be reserved.
Table 30.
Bit
Mnemonic
Function
VRAS
Variable Rate PCM Audio
Support (Read-Only)
SPDIF
SPDIF Support (Read-Only)
This bit returns a 1 when Read To indicates that the SPDIF transmitter is supported (IEC958).
This bit is also used to validate that the SPDIF transmitter output is enabled. The SPDIF bit can
be set high only if the SPDIF pin (Pin 48) is pulled down at power-up, enabling the codec
transmitter logic. If the SPDIF pin is floating or pulled high at power-up, the transmitter logic
is disabled; therefore, this bit returns a low, indicating that the SPDIF transmitter is not
available. This bit must always be read back to verify that the SPDIF transmitter is actually
enabled.
DSA [1:0]
DAC Slot Assignments
(Read/Write)
00 DACs 1, 2 = 3 and 4.
01 DACs 1, 2 = 7 and 8.
10 DACs 1, 2 = 6 and 9.
11 Reserved.
AMAP
Slot DAC Mappings Based
on Codec ID (Read-Only)
supported.
REVC [1:0]
AC ’97 Revision Compliance
REVC [1:0] = 01 indicates that the codec is AC ’97 revision 2.2-compliant (read-only).
IDC [1:0]
Indicates Codec
Configuration (Read-Only)
01, 10, 11 = Secondary.
Name
Ext’d Audio ID
D15
IDC1
D14
IDC0
D13
X
D12
X
D11
REVC1
D10
REVC0
D9
AMAP
D8
X
D7
X
D6
X
D5
DSA1
D4
DSA0
D3
X
D2
SPDIF
D1
X
D0
VRAS
Default
0xX605
This bit returns a 1 when Read To indicates that the variable rate PCM audio is supported.
Reset default = 00.
This bit returns a 1 when read to indicate that slot/DAC mappings based on the codec ID are
00 = Primary.
EXTENDED AUDIO STATUS AND CONTROL REGISTER
Index 0x2A
Reg
No.
0x2A
Name
Ext’d Audio
Stat/Ctrl
D15
VFORCE
D14
X
D13
X
D12
X
D11
X
D10
SPCV
D9
X
D8
X
D7
X
D6
X
D5
SPSA1
D4
SPSA0
D3
X
D2
SPDIF
D1
X
D0
VRA
Default
0x0000
The extended audio status and control register is a read/write register that provides status and control of the extended audio features.
All registers are not shown, and bits containing an X are assumed to be reserved.
Table 31.
Bit
Mnemonic
Function
VRA
Variable Rate Audio
(Read/Write)
VRA = 1 enables variable rate audio mode (enables sample rate registers and SLOTREQ
signaling).
SPDIF
SPDIF Transmitter
Subsystem Enable/Disable
Bit (Read/Write)
This bit is also used to validate that the SPDIF transmitter output is enabled. The SPDIF bit can
be set high only if the SPDIF pin (Pin 48) is pulled down at power-up, enabling the codec
transmitter logic. If the SPDIF pin is floating or pulled high at power-up, the transmitter logic is
disabled and this bit returns a low, indicating that the SPDIF transmitter is not available. This bit
must always be read back to verify that the SPDIF transmitter is enabled.
SPSA [1:0]
SPDIF Slot Assignment Bits
(Read/Write)
ID configuration.
VRA = 0 sets the fixed sample rate audio to 48 kHz (reset default).
SPDIF = 1 enables the SPDIF transmitter.
SPDIF = 0 disables the SPDIF transmitter (default).
These bits control the SPDIF slot assignment and respective defaults, depending on the codec
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