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參數(shù)資料
| 型號： | ADS807E |
| 英文描述： | 12-Bit, 53MHz Sampling ANALOG-TO-DIGITAL CONVERTER |
| 中文描述： | 12位，53MHz采樣模擬數(shù)字轉(zhuǎn)換器 |
| 文件頁數(shù)： | 14/15頁 |
| 文件大?。?/td> | 225K |
| 代理商： | ADS807E |
14
ADS807
INPUT
REFERENCE
IN (Pin-25)
IN (Pin-24)
REFT
REFB
2Vp-p Differential
1Vp-p Times 2 Inputs
Internal
or External
2V to 3V
3V to 2V
+3V
+2V
2Vp-p Single-Ended
2Vp-p Times 1 Input
Internal
or External
1.5V to 3.5V
2.5V
DC
+3V
+2V
3Vp-p Differential
1.5Vp-p Times 2 Inputs
Internal
or External
1.75V to 3.35V
3.25V to 1.75V +3.25V +1.75V
3Vp-p Single-Ended
3Vp-p Times 1 Input
Internal
or External
1V to 4V
2.5V
DC
+3.25V +1.75V
TABLE III. Coding Table for Single-Ended Input Config-
uration with IN Tied to the Common-Mode
Voltage.
TABLE II. Coding Table for Single-Ended Input Configura-
tion with IN Tied to the Common-Mode Voltage.
DIGITAL INPUTS AND OUTPUTS
Clock Input Requirements
Clock jitter is critical to the SNR performance of high speed,
high resolution A/D converters. Clock jitter leads to aperture
jitter (t
A
), which adds noise to the signal being converted. The
ADS807 samples the input signal on the rising edge of the
CLK input. Therefore, this edge should have the lowest
possible jitter. The jitter noise contribution to total SNR is
given by the following equation. If this value is near your
system requirements, input clock jitter must be reduced.
where:
IN
is input signal frequency
t
A
is rms clock jitter
Particularly in undersampling applications, special consider-
ation should be given to clock jitter. The clock input should
be treated as an analog input in order to achieve the highest
level of performance. Any overshoot or undershoot of the
clock signal may cause degradation of the performance.
When digitizing at high sampling rates, the clock should
have 50% duty cycle (t
H
= t
L
), along with fast rise and fall
times of 2ns or less.
Over Range Indicator (OTR)
If the analog input voltage exceeds the set full-scale range,
an over range condition exists. The ‘OTR’ pin of the ADS807
can be used to monitor any such out-of-range condition. This
‘OTR’ output is updated along with the data output corre-
sponding to the particular sampled analog input voltage.
Therefore, the OTR data is subject to the same pipeline
delay as the digital data. The OTR output is LOW when the
input voltage is within the defined input range. It will go to
HIGH if the applied signal exceeds the full-scale range.
Data Outputs
The output data format of the ADS807 is in positive Straight
Offset Binary code, see Table II and Table II. This format
can easily be converted into the Two’s Binary Complement
code by inverting the MSB.
It is recommended that the capacitive loading on the data
lines be as low as possible (< 15pF). Higher capacitive
loading will cause larger dynamic currents as the digital
outputs are changing. Those high current surges can feed
back to the analog portion of the ADS807 and affect the
performance. If necessary, external buffers or latches close
SINGLE-ENDED INPUT
(IN = CM, Pin-23)
STRAIGHT OFFSET BINARY
(SOB)
+FS–1LSB (IN = CMV + FSR/2)
+1/2 FS
Bipolar Zero (IN = V
CM
)
–1/2 FS
–FS (IN = CMV – FSR/2)
1111 1111 1111
1100 0000 0000
1000 0000 0000
0100 0000 0000
0000 0000 0000
STRAIGHT OFFSET BINARY
(SOB)
DIFFERENTIAL INPUT
+FS-1LSB (IN = +3V, IN = +2V)
+1/2 FS
Bipolar Zero (IN = IN = V
CM
)
–1/2 FS
–FS (IN = +2V, IN = +3V)
1111 1111 1111
1100 0000 0000
1000 0000 0000
0100 0000 0000
0000 0000 0000
JitterSNR
t
rmssignaltormsnoise
IN
A
=
20
1
2
log
π
TABLE I. Reference Voltages for Input Signal Ranges.
to the converter’s output pins may be used to minimize the
capacitive loading. They also provide the added benefit of
isolating the ADS807 from high frequency digital noise on
the bus coupling back into the converter.
Digital Output Driver Supply (VDRV)
The ADS807 features a dedicated supply pin for the output
logic drivers, VDRV, which is not internally connected to
the other supply pins. Setting the voltage at VDRV to +5V
or +3V, the ADS807 produces corresponding logic levels
and can directly interface to the selected logic family. The
output stages are designed to supply sufficient current to
drive a variety of logic families. However, it is recom-
mended to use the ADS807 with +3V logic supply. This will
lower the power dissipation in the output stages due to the
lower output swing and reduce current glitches on the supply
line which may affect the AC performance of the converter.
In some applications, it might be advantageous to decouple
the VDRV pin with additional capacitors or a pi-filter.
GROUNDING AND DECOUPLING
Proper grounding, bypassing, short trace lengths, and the use
of power and ground planes are particularly important for
high frequency designs. Multilayer PC boards are recom-
mended for best performance since they offer distinct advan-
tages such as minimizing ground impedance, separation of
signal layers by ground layers, etc. The ADS807 should be
treated as an analog component. Whenever possible, the
supply pins should be powered by the analog supply. This
will ensure the most consistent results, since digital supply
lines often carry high levels of noise which otherwise would
be coupled into the converter and degrade the achievable
performance. All ground connections on the ADS807 are
internally joined together obviating the design of split ground
planes. The ground pins (1, 20, 26) should directly connect
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| ADS807E/1K | 功能描述:模數(shù)轉(zhuǎn)換器 - ADC 12-Bit 53 MSPS SE/Diff imputs RoHS:否 制造商:Texas Instruments 通道數(shù)量:2 結(jié)構(gòu):Sigma-Delta 轉(zhuǎn)換速率:125 SPs to 8 KSPs 分辨率:24 bit 輸入類型:Differential 信噪比:107 dB 接口類型:SPI 工作電源電壓:1.7 V to 3.6 V, 2.7 V to 5.25 V 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:VQFN-32 |
| ADS807E/1KG4 | 功能描述:模數(shù)轉(zhuǎn)換器 - ADC 12-Bit 53 MSPS SE/Diff imputs RoHS:否 制造商:Texas Instruments 通道數(shù)量:2 結(jié)構(gòu):Sigma-Delta 轉(zhuǎn)換速率:125 SPs to 8 KSPs 分辨率:24 bit 輸入類型:Differential 信噪比:107 dB 接口類型:SPI 工作電源電壓:1.7 V to 3.6 V, 2.7 V to 5.25 V 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:VQFN-32 |
| ADS807EG4 | 功能描述:模數(shù)轉(zhuǎn)換器 - ADC 12-Bit 53 MSPS SE/Diff imputs RoHS:否 制造商:Texas Instruments 通道數(shù)量:2 結(jié)構(gòu):Sigma-Delta 轉(zhuǎn)換速率:125 SPs to 8 KSPs 分辨率:24 bit 輸入類型:Differential 信噪比:107 dB 接口類型:SPI 工作電源電壓:1.7 V to 3.6 V, 2.7 V to 5.25 V 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:VQFN-32 |
| ADS808 | 制造商:BB 制造商全稱:BB 功能描述:12-Bit, 70MHz Sampling ANALOG-TO-DIGITAL CONVERTER |
| ADS808Y/250 | 功能描述:模數(shù)轉(zhuǎn)換器 - ADC 12-Bit 70MHz Sampling ADC RoHS:否 制造商:Texas Instruments 通道數(shù)量:2 結(jié)構(gòu):Sigma-Delta 轉(zhuǎn)換速率:125 SPs to 8 KSPs 分辨率:24 bit 輸入類型:Differential 信噪比:107 dB 接口類型:SPI 工作電源電壓:1.7 V to 3.6 V, 2.7 V to 5.25 V 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:VQFN-32 |
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