參數(shù)資料
型號(hào): ADS7864YB
英文描述: 500kHz, 12-Bit, 6-Channel Simultaneous Sampling ANALOG-TO-DIGITAL CONVERTER
中文描述: 為500kHz,12位,6通道同步采樣模擬到數(shù)字轉(zhuǎn)換器
文件頁(yè)數(shù): 14/16頁(yè)
文件大小: 183K
代理商: ADS7864YB
14
ADS7864
At time t
A
(Figure 13) the ADS7864 resets. With the reset
signal all conversions and scheduled conversions are can-
celled. The data in the output registers are also cleared. With
a reset a running conversion gets interrupted and all chan-
nels go into the sample mode again.
At time t
B
a HOLDB signal occurs. With the next falling
clock edge (t
C
) the ADS7864 puts channel B into the loop to
be converted next. As the reset signal occurred at t
A
, the
conversion of channel B will be started with the next rising
edge of the clock after t
C
.
Within the next clock cycle (t
C
to t
F
), HOLDC (t
D
) and
HOLDA (t
E
) occur. If more than one hold signals get active
within one clock cycle, channel A will be converted first. So
as soon as the conversion of channel B is done, the conver-
sion of channel A will be initiated. After this second conver-
sion, channel C will be converted.
RESET
CLOCK
HOLDA
HOLDB
HOLDC
t
A
t
B
t
C
t
D
t
E
t
F
The 16 bit output word has following structure:
Bit 15 shows if the FIFO is empty (low) or if it contains
channel information (high). Bit 12 to 14 contain the Channel
for the 12 bit data word (Bit 0 to 11). If the data is from
channel A0, then bits 14 to 12 are 000. The Channel bit
pattern is outlined in Table I (Channel Truth Table).
New data is always written into the next available register. At
t
0
(see Figure 14), the reset deletes all the existing data. At t
1
the new data of the channels A0 and A1 are put into registers
0 and 1. On t
2
the read process of channel A0 data is finished.
Therefore this data is dumped and A1 data is shifted to register
0. At t
3
new data is available, this time from channel B0 and
B1. This data is written into the next available registers
(register 1 and 2). The new data of channel C0 and C1 at t
4
is
put on top (registers 3 and 4).
FIGURE 13. Example of Hold Signals.
FIGURE 14. Functionality Diagram of FIFO Registers.
Valid
Data
3-Bit Channel
Information
12-Bit Data Word
RESET
BUSY
Conversion
Channel A
empty
empty
empty
empty
empty
empty
Conversion
Channel B
Conversion
Channel C
RD
t
0
t
1
t
2
t
3
reg. 5
reg. 4
reg. 2
reg. 3
reg. 1
reg. 0
empty
empty
empty
empty
ch A1
ch A0
empty
empty
empty
ch B1
ch B0
ch A1
empty
empty
empty
empty
empty
ch A1
empty
ch C1
ch C0
ch B1
ch B0
ch A1
t
4
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ADS7864YB/2KG4 功能描述:模數(shù)轉(zhuǎn)換器 - ADC 500kHz 12-Bit 6-Ch Simltns Smplng ADC RoHS:否 制造商:Texas Instruments 通道數(shù)量:2 結(jié)構(gòu):Sigma-Delta 轉(zhuǎn)換速率:125 SPs to 8 KSPs 分辨率:24 bit 輸入類型:Differential 信噪比:107 dB 接口類型:SPI 工作電源電壓:1.7 V to 3.6 V, 2.7 V to 5.25 V 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:VQFN-32
ADS7865 制造商:TI 制造商全稱:Texas Instruments 功能描述:Dual, 12-Bit, 3+3 or 2+2 Channel, Simultaneous Sampling Analog-to-Digital Converter