參數(shù)資料
型號(hào)： ADS7864YB
英文描述： 500kHz, 12-Bit, 6-Channel Simultaneous Sampling ANALOG-TO-DIGITAL CONVERTER
中文描述： 為500kHz，12位，6通道同步采樣模擬到數(shù)字轉(zhuǎn)換器
文件頁(yè)數(shù)： 10/16頁(yè)
文件大小： 183K
代理商： ADS7864YB
10
ADS7864
THEORY OF OPERATION
The ADS7864 contains two 12-bit A/D converters that operate
simultaneously. The three hold signals (HOLDA, HOLDB,
HOLDC) select the input MUX and initiate the conversion. A
simultaneous hold on all six channels can occur with all three
hold signals strobed together. The converted values are saved
in 6 registers. For each read operation the ADS7864 outputs
16 bits of information (12 Data, 3 Channel Address and Data
Valid). The Address/Mode signals (A0, A1, A2) select how
the data is read from the ADS7864. These Address/Mode
signals can define a selection of a single channel, a cycle mode
that cycles through all channels or a FIFO mode that se-
quences the data determined by the order of the Hold signals.
The FIFO mode will allow the 6 registers to be used by a
single channel pair and therefore three locations for CH X0
and three locations for CH X1 can be acquired before they are
read from the part.
EXPLANATION OF CLOCK, RESET
AND BUSY PINS
CLOCK—
An external clock has to be provided for the
ADS7864. The maximum clock frequency is 8MHz. The
minimum clock cycle is 125ns (Figure 8, t
5
), and the clock
has to remain HIGH (Figure 8, t
6
) or LOW (Figure 8, t
7
) for
at least 40ns.
RESET
—Bringing reset LOW will reset the ADS7864. It
will clear all the output registers, stop any actual conversions
and will close the sampling switches. Reset has to stay LOW
for at least 20ns (Figure 8, t
8
). The reset should be back
HIGH for at least 20ns (Figure 8, t
9
), before starting the next
conversion (negative hold edge).
BUSY
—Busy goes LOW when the internal A/D converters
start a new conversion. It stays LOW as long as the conver-
sion is in progress (Figure 9, 13 clock-cycles, t
10
) and rises
again, after the data is latched to the output register. With
busy going high, the new data can be read. It takes at least
16 clock cycles (Figure 9, t
11
) to complete conversion.
Code (decimal)
8000
7000
6000
5000
4000
3000
2000
1000
0
N
2044
2045
2046
2047
2048
FIGURE 5. Histogram of 8,000 Conversions of a DC Input.
FIGURE 6. Test Circuits for Timing Specifications.
FIGURE 7. Level Shift Circuit for Bipolar Input Ranges.
TRANSITION NOISE
Figure 5 shows a histogram plot for the ADS7864 following
8,000 conversions of a DC input. The DC input was set at
output code 2046. All but one of the conversions had an
output code result of 2046 (one of the conversions resulted
in an output of 2047). The histogram reveals the excellent
noise performance of the ADS7864.
BIPOLAR INPUTS
The differential inputs of the ADS7864 were designed to
accept bipolar inputs (–V
REF
and +V
REF
) around the internal
reference voltage (2.5V), which corresponds to a 0V to 5V
input range with a 2.5V reference. By using a simple op amp
circuit featuring a single amplifier and four external resis-
tors, the ADS7864 can be configured to except bipolar
inputs. The conventional
±
2.5V,
±
5V, and
±
10V input
ranges can be interfaced to the ADS7864 using the resistor
values shown in Figure 7.
TIMING AND CONTROL
The ADS7864 uses an external clock (CLOCK, pin 22)
which controls the conversion rate of the CDAC. With an
8MHz external clock, the A/D sampling rate is 500kHz
which corresponds to a 2
μ
s maximum throughput time.
R
1
R
2
+IN
–IN
REF
OUT
(pin 33)
2.5V
4k
20k
Bipolar Input
BIPOLAR INPUT
±
10V
±
5V
±
2.5V
R
1
1k
2k
4k
R
2
5k
10k
20k
OPA340
ADS7864
DATA
1.4V
Test Point
3k
100pF
C
LOAD
t
R
DATA
Voltage Waveforms for DATA Rise and Fall Times t
R
, and t
F
.
V
OH
V
OL
t
F
相關(guān)PDF資料
PDF描述
ADS7864 500kHz, 12-Bit, 6-Channel Simultaneous Sampling ANALOG-TO-DIGITAL CONVERTER
ADS7883 16-BIT, 1-MSPS, PSEUDO-BIPOLAR, FULLY DIFFERENTIAL INPUT, MICROPOWER SAMPLING ANALOG-TO-DIGITAL CONVERTER WITH PARALLEL INTERFACE, REFERENCE
ADS8405 16-BIT, 1-MSPS, PSEUDO-BIPOLAR, FULLY DIFFERENTIAL INPUT, MICROPOWER SAMPLING ANALOG-TO-DIGITAL CONVERTER WITH PARALLEL INTERFACE, REFERENCE
ADS8410 16-BIT, 1-MSPS, PSEUDO-BIPOLAR, FULLY DIFFERENTIAL INPUT, MICROPOWER SAMPLING ANALOG-TO-DIGITAL CONVERTER WITH PARALLEL INTERFACE, REFERENCE
ADS8413 16-BIT, 1-MSPS, PSEUDO-BIPOLAR, FULLY DIFFERENTIAL INPUT, MICROPOWER SAMPLING ANALOG-TO-DIGITAL CONVERTER WITH PARALLEL INTERFACE, REFERENCE
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
ADS7864YB/250 功能描述:模數(shù)轉(zhuǎn)換器 - ADC 500kHz 12-Bit 6-Ch Simltns Smplng ADC RoHS:否 制造商:Texas Instruments 通道數(shù)量:2 結(jié)構(gòu):Sigma-Delta 轉(zhuǎn)換速率:125 SPs to 8 KSPs 分辨率:24 bit 輸入類型:Differential 信噪比:107 dB 接口類型:SPI 工作電源電壓:1.7 V to 3.6 V, 2.7 V to 5.25 V 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:VQFN-32
ADS7864YB/250G4 功能描述:模數(shù)轉(zhuǎn)換器 - ADC 500kHz 12-Bit 6-Ch Simltns Smplng ADC RoHS:否 制造商:Texas Instruments 通道數(shù)量:2 結(jié)構(gòu):Sigma-Delta 轉(zhuǎn)換速率:125 SPs to 8 KSPs 分辨率:24 bit 輸入類型:Differential 信噪比:107 dB 接口類型:SPI 工作電源電壓:1.7 V to 3.6 V, 2.7 V to 5.25 V 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:VQFN-32
ADS7864YB/2K 功能描述:模數(shù)轉(zhuǎn)換器 - ADC 500kHz 12-Bit 6-Ch Simltns Smplng ADC RoHS:否 制造商:Texas Instruments 通道數(shù)量:2 結(jié)構(gòu):Sigma-Delta 轉(zhuǎn)換速率:125 SPs to 8 KSPs 分辨率:24 bit 輸入類型:Differential 信噪比:107 dB 接口類型:SPI 工作電源電壓:1.7 V to 3.6 V, 2.7 V to 5.25 V 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:VQFN-32
ADS7864YB/2KG4 功能描述:模數(shù)轉(zhuǎn)換器 - ADC 500kHz 12-Bit 6-Ch Simltns Smplng ADC RoHS:否 制造商:Texas Instruments 通道數(shù)量:2 結(jié)構(gòu):Sigma-Delta 轉(zhuǎn)換速率:125 SPs to 8 KSPs 分辨率:24 bit 輸入類型:Differential 信噪比:107 dB 接口類型:SPI 工作電源電壓:1.7 V to 3.6 V, 2.7 V to 5.25 V 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:VQFN-32
ADS7865 制造商:TI 制造商全稱:Texas Instruments 功能描述:Dual, 12-Bit, 3+3 or 2+2 Channel, Simultaneous Sampling Analog-to-Digital Converter
發(fā)布緊急采購(gòu)，3分鐘左右您將得到回復(fù)。

采購(gòu)需求

(若只采購(gòu)一條型號(hào)，填寫(xiě)一行即可)

發(fā)布成功！您可以繼續(xù)發(fā)布采購(gòu)。也可以進(jìn)入我的后臺(tái)，查看報(bào)價(jià)

發(fā)布成功！您可以繼續(xù)發(fā)布采購(gòu)。也可以進(jìn)入我的后臺(tái)，查看報(bào)價(jià)

*型號(hào) *數(shù)量 廠商 批號(hào) 封裝
添加更多采購(gòu)

我的聯(lián)系方式

*
*
*