參數(shù)資料
型號: ADS7864YB
英文描述: 500kHz, 12-Bit, 6-Channel Simultaneous Sampling ANALOG-TO-DIGITAL CONVERTER
中文描述: 為500kHz,12位,6通道同步采樣模擬到數(shù)字轉(zhuǎn)換器
文件頁數(shù): 11/16頁
文件大?。?/td> 183K
代理商: ADS7864YB
11
ADS7864
START OF A CONVERSION
By bringing one or all of the HOLDX signals low, the input
data of the corresponding channel X is immediately placed
in the hold mode (5ns). The conversion of this channel X
follows as soon as the AD-converter is available for the
particular channel. If other channels are already in the hold
mode but not converted, then the conversion of channel X is
put in the queue until the previous conversion has been
completed. If more than one channel goes into hold mode
within one clock cycle, then channel A will be converted
first if HOLDA is one of the triggered hold signals. Next
channel B will be converted and at last channel C. If it
is important to detect a hold command during a certain
clock-cycle, then the falling edge of the hold signal has to
occur at least 10ns before the falling edge of clock. (Figure
8, t
1
). The hold signal can remain low without initiating a
new conversion. The hold signal has to be high for at least
15ns (Figure 8, t
2
) before it is brought low again and hold
has to stay low for at least 20ns (Figure 8, t
3
).
CLOCK
HOLDA
HOLDB
HOLDC
RESET
t
9
t
1
t
6
t
8
t
2
t
3
t
5
t
7
In the example of Figure 8, the signal HOLDB goes low first
and channel B0 and B1 will be converted first. The falling
edges of HOLDA and HOLDC occur within the same clock
cycle. Therefore, the channels A0 and A1 will be converted
as soon as the channels B0 and B1 are finished (plus
acquisition time). When the A-channels are finished, the
C-channels will be converted. The second HOLDA signal is
ignored, as the A-channels are not converted at this point in
time.
Once a particular hold signal goes low, further impulses of
this hold signal are ignored until the conversion is finished
or the part is reset. When the conversion is finished (BUSY
signal goes high) the sampling switches will close and
sample the selected channel. The start of the next conversion
must be delayed to allow the input capacitor of the ADS7864
to be fully charged. This delay time depends on the driving
amplifier, but should be at least 175ns (Figure 9, t
4
).
The ADS7864 can also convert one channel continuously, as
it is shown in Figure 9 with channel B. Therefore, HOLDA
and HOLDC are kept high all the time. To gain acquisition
FIGURE 8. Start of the Conversion.
SYMBOL
DESCRIPTION
MIN
TYP
MAX
UNITS
t
1
HOLD (A, B, C) before
falling edge of clock
10
ns
t
2
HOLD HIGH time to be
recognized again
15
ns
t
3
t
4
t
5
t
6
t
7
t
8
t
9
t
10
t
11
t
12
t
13
t
14
HOLD LOW time
20
ns
Input capacitor charge time
175
ns
Clock period
125
ns
Clock HIGH time
40
ns
Clock LOW time
40
ns
Reset pulse width
20
ns
First hold after reset
20
ns
Conversion time
12.5 t
5
ns
μ
s
ns
Successive conversion time (16 t
5
)
Address setup before RD
2
10
CS before end of RD
30
ns
RD HIGH time
30
ns
TIMING SPECIFICATIONS
FIGURE 9. Timing of One Conversion Cycle.
BUSY
CLOCK
HOLDB
CS
RD
A0
t
4
t
10
t
11
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