參數(shù)資料
型號(hào)： ADS6242IRGZTG4
廠商： TEXAS INSTRUMENTS INC
元件分類： ADC
英文描述： 2-CH 14-BIT PROPRIETARY METHOD ADC, SERIAL ACCESS, PQCC48
封裝： 7 X 7 MM, GREEN, PLASTIC, QFN-48
文件頁(yè)數(shù)： 8/76頁(yè)
文件大?。?/td> 3497K
代理商： ADS6242IRGZTG4
www.ti.com
SERIAL INTERFACE TIMING CHARACTERISTICS
RESET TIMING
T0108-03
t
1
t
3
t
2
PowerSupply
AVDD,LVDD
RESET
SEN
SLAS542A – MAY 2007 – REVISED JULY 2007
Typical values at 25
°C, min and max values across the full temperature range T
MIN = –40°C to TMAX = 85°C, AVDD = LVDD =
3.3V, unless otherwise noted.
PARAMETER
MIN
TYP
MAX
UNIT
fSCLK
SCLK Frequency, fSCLK = 1/tSCLK
> DC
20
MHz
tSLOADS
SEN to SCLK Setup time
25
ns
tSLOADH
SCLK to SEN Hold time
25
ns
tDSU
SDATA Setup time
25
ns
tDH
SDATA Hold time
25
ns
Time taken for register write to take effect after 16th SCLK falling edge
100
ns
Typical values at 25
°C, min and max values across the full temperature range T
MIN = –40°C to TMAX = 85°C, AVDD = LVDD =
3.3V, unless otherwise noted.
PARMATER
CONDITIONS
MIN
TYP
MAX
UNIT
t1
Power-on delay time
Delay from power-up of AVDD and LVDD to RESET pulse active
5
ms
t2
Reset pulse width
Pulse width of active RESET signal
10
ns
t3
Register write delay time
Delay from RESET disable to SEN active
25
ns
tPO
Power-up delay time
Delay from power-up of AVDD and LVDD to output stable
6.5
ms
Figure 5. Reset Timing
16
Copyright 2007, Texas Instruments Incorporated
Product Folder Link(s): ADS6245 ADS6244 ADS6243 ADS6242
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