參數(shù)資料
型號(hào)： ADS6242IRGZTG4
廠商： TEXAS INSTRUMENTS INC
元件分類： ADC
英文描述： 2-CH 14-BIT PROPRIETARY METHOD ADC, SERIAL ACCESS, PQCC48
封裝： 7 X 7 MM, GREEN, PLASTIC, QFN-48
文件頁數(shù)： 42/76頁
文件大?。?/td> 3497K
代理商： ADS6242IRGZTG4
www.ti.com
CLOCK INPUT
SLAS542A – MAY 2007 – REVISED JULY 2007
So, the fine gain can be used to trade-off between SFDR and SNR. The coarse gain makes it possible to get
best SFDR but without losing SNR significantly. At high input frequencies, the gains are especially useful as the
SFDR improvement is significant with marginal degradation in SINAD.
The gains can be programmed using the register bits <COARSE GAIN> (Table 19) and <FINE GAIN>
(Table 18). Note that the default gain after reset is 0 dB.
Table 22. Full-Scale Range Across Gains
GAIN, dB
TYPE
FULL-SCALE, Vpp
0
Default (after reset)
2
3.5
Coarse setting (fixed)
1.34
1
1.78
2
1.59
3
1.42
Fine setting (programmable)
4
1.26
5
1.12
6
1.00
The ADS624X clock inputs can be driven differentially (SINE, LVPECL or LVDS) or single-ended (LVCMOS),
with little or no difference in performance between them. The common-mode voltage of the clock inputs is set to
VCM using internal 5-k
resistors as shown in Figure 89. This allows using transformer-coupled drive circuits for
sine wave clock or ac-coupling for LVPECL, LVDS clock sources (see Figure 91 and Figure 93). Figure 90
shows the impedance looking into the clock input pins of the device.
Copyright 2007, Texas Instruments Incorporated
47
Product Folder Link(s): ADS6245 ADS6244 ADS6243 ADS6242
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