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參數(shù)資料
| 型號： | ADS5413IPHP |
| 廠商： | Texas Instruments, Inc. |
| 英文描述： | SINGLE 12-BIT, 65-MSPS IF SAMPLING ANALOG-TO-DIGITAL CONVERTER |
| 中文描述： | 單12位，65 MSPS的中頻采樣模擬到數(shù)字轉(zhuǎn)換器 |
| 文件頁數(shù)： | 6/18頁 |
| 文件大小： | 421K |
| 代理商： | ADS5413IPHP |
ADS5413
SLWS153 DECEMBER 2003
www.ti.com
14
The ADS5413 can be driven either with a sine wave or a
square wave. The internal ADC core uses both edges of
the clock for the conversion process. This means that
ideally, a 50% duty cycle should be provided.
Nevertheless, the ADC includes an on-board duty cycle
adjuster (DCA) that adjusts the incoming clock duty cycle
which may not be 50%, to a 50% duty cycle for the internal
use. By default, this circuit is enabled internally (with a
pull-up resistor of 70 k
), which relaxes the design
specifications of the external clock. Figure 16 shows the
performance of the ADC for a 65-MHz clock and 14-MHz
input signal versus clock duty cycle, for the two cases, with
the DCA enabled and disabled. Nevertheless, there are
some situations where the user may prefer to disable the
DCA. For asynchronous clocking, i.e., when the sampling
period is purposely not constant, this circuit should be
disabled. Another situation is the case of high input
frequency sampling. For high input frequencies, a low jitter
clock should be provided. On that sense, we recommend
to band-pass filter the source which, consequently,
provides a sinusoidal clock with 50% duty cycle. The use
of the DCA on that case would not be beneficial and adds
noise to the internal clock, increasing the jitter and
degrading the performance. Figure 19 shows the
performance versus input frequency for the different
clocking schemes. Finally, adding the DCA introduces
delay between the input clock and the output data and
what is more important, slightly bigger variation of this
delay versus external conditions, such as temperature. To
disable the DCA, user should connect it to ground.
POWER DOWN
When power down (pin 16) is tied to AVDD, the device
reduces its power consumption to a typical value of
23 mW. Connecting this pin to GND or leaving it not
connected (an internal 70-k
pulldown resistor is
provided) enables the device operation.
DIGITAL OUTPUTS
The ADS5413 output format is 2s complement. The
voltage level of the outputs can be adjusted by setting the
OVDD voltage between 1.6 V and 3.6 V, allowing for direct
interface
to
several
digital
families.
For
better
performance, customers should select the smaller output
swing required in the application. To improve the
performance, mainly on the higher output voltage swing
configurations, the addition of a series resistor at the
outputs, limiting peak currents, is recommended. The
maximum value of this resistor is limited by the maximum
data rate of the application. Values between 0
and
200
are usual. Also, limiting the length of the external
traces is a good practice.
All the data sheet plots have been obtained in the worst
case situation, where OVDD is 3.3 V. The external series
resistors were 150
and the load was a 74AVC16244
buffer, as the one used in the evaluation board. In this
configuration, the rising edge of the ADC output is 5 ns,
which allows for a window to capture the data of 10.4 ns
(without including other factors).
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參數(shù)描述 |
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| ADS5413IPHPG4 | 功能描述:模數(shù)轉(zhuǎn)換器 - ADC Lo-Pwr Anlg to Dig Converter RoHS:否 制造商:Texas Instruments 通道數(shù)量:2 結(jié)構(gòu):Sigma-Delta 轉(zhuǎn)換速率:125 SPs to 8 KSPs 分辨率:24 bit 輸入類型:Differential 信噪比:107 dB 接口類型:SPI 工作電源電壓:1.7 V to 3.6 V, 2.7 V to 5.25 V 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:VQFN-32 |
| ADS5421 | 制造商:BB 制造商全稱:BB 功能描述:14-Bit, 40MHz Sampling ANALOG-TO-DIGITAL CONVERTER |
| ADS5421EVM | 功能描述:數(shù)據(jù)轉(zhuǎn)換 IC 開發(fā)工具 ADS5421 Evaluation Module RoHS:否 制造商:Texas Instruments 產(chǎn)品:Demonstration Kits 類型:ADC 工具用于評估:ADS130E08 接口類型:SPI 工作電源電壓:- 6 V to + 6 V |
| ADS5421K5 | 制造商:TI 制造商全稱:Texas Instruments 功能描述:14-Bit, 62MSPS Sampling ANALOG-TO-DIGITAL CONVERTER |
| ADS5421R | 制造商:BB 制造商全稱:BB 功能描述:14-Bit, 40MHz Sampling ANALOG-TO-DIGITAL CONVERTER |
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