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參數(shù)資料
| 型號： | ADS5413IPHP |
| 廠商： | Texas Instruments, Inc. |
| 英文描述： | SINGLE 12-BIT, 65-MSPS IF SAMPLING ANALOG-TO-DIGITAL CONVERTER |
| 中文描述： | 單12位，65 MSPS的中頻采樣模擬到數(shù)字轉(zhuǎn)換器 |
| 文件頁數(shù)： | 13/18頁 |
| 文件大?。?/td> | 421K |
| 代理商： | ADS5413IPHP |
ADS5413
SLWS153 DECEMBER 2003
www.ti.com
4
ELECTRICAL CHARACTERISTICS (CONTINUED)
over operating free-air temperature range, clock frequency = 65 MSPS, 50% clock duty cycle (AVDD = OVDD = 3.3 V), duty cylce adjust off,
internal reference, AIN = 1 dBFS, 1.2-VPP square differential clock (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
AC PERFORMANCE (Continued)
fIN = 14 MHz
90
fIN = 39 MHz
90
HD2
Second order harmonic
fIN = 70 MHz
90
dBc
HD2
Second order harmonic
fIN = 150 MHz
83
dBc
fIN = 220 MHz
72
fIN = 14 MHz
77.5
fIN = 39 MHz
79
HD3
Third order harmonic
fIN = 70 MHz
81
dBc
HD3
Third order harmonic
fIN = 150 MHz
69
dBc
fIN = 220 MHz
77
Two tone IMD rejection, A1,2 = 7 dBFS
f1 = 220 MHz,
f2 = 225 MHz
69
dBc
Analog input bandwidth
3 dB BW respect to 3 dBFS input at low
frequency
1
GHz
TIMING CHARACTERISTICS
25
°C, CL = 10 pF
MIN
TYP
MAX
UNIT
t
Aperture delay
2
ns
td(A)
Aperture jitter
0.4
ps
td(Pipe)
Latency
6
Cycles
td1
Propagation delay from clock input to beginning of data stable(1)
DCS off OVDD 1 8 V
8
ns
td2
Propagation delay from clock input to end of data stable(1)
DCS off, OVDD = 1.8 V
20.3
ns
td1
Propagation delay from clock input to beginning of data stable(1)
DCS off OVDD 3 3 V
7
ns
td2
Propagation delay from clock input to end of data stable(1)
DCS off, OVDD = 3.3 V
20.3
ns
td1
Propagation delay from clock input to beginning of data stable(1)
DCS on OVDD 1 8 V
10
ns
td2
Propagation delay from clock input to end of data stable(1)
DCS on, OVDD = 1.8 V
22.3
ns
td1
Propagation delay from clock input to beginning of data stable(1)
DCS on OVDD 3 3 V
9
ns
td2
Propagation delay from clock input to end of data stable(1)
DCS on, OVDD = 3.3 V
22.3
ns
(1) Data stable if VO < 10% OVDD or VO > 90% OVDD
TIMING DIAGRAM
VINP
CLK
D[0:11]
Data N7
tw(H)
tw(L)
td(A)
Sample N
tc
td2(O)
td(Pipe)
Data N6
Data N5
Data N4
Data N3
Data N2
Data N1
Data N
Data N+1
Data N+2
td1(O)
Figure 1. ADS5413 Timing Diagram
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