
ADS5413
SLWS153 DECEMBER 2003
www.ti.com
13
Another possibility is the use of differential input/output
amplifiers that can simplify the driver circuit for applications
requiring input dc coupling. Flexible in their configurations
(see
Figure 32), such amplifiers can be used for single ended
to differential conversion, for signal amplification, and for
filtering prior to the ADC.
+
+
VOCM
12 Bit/80 MSPS
IN
5 V
CML
5 V
VS
10
F
0.1
F
10
F 0.1 F
THS4503
Rf
CF
1
F
Rg
0.1
F
RT
RS
ADS5413
Figure 32. Using the THS4503 With the ADS5413
REFERENCE CIRCUIT
The ADS5413 has its own internal reference generation
saving external circuitry in the design. For optimum
performance, it is best to connect both VREFB and VREFT
to ground with a 1-
F and a 0.1-F decoupling capacitor
in parallel and a 0.1-
F capacitor between both pins (see
Figure 33). The band-gap voltage output is not a voltage
source to be used external to the ADS5413. However, it
should be decoupled to ground with a 1-
F and a 0.01-F
capacitor in parallel.
For even more design flexibility, the internal reference can
be disabled using the pin 48. By default, this pin is
internally connected with a 70-k
pulldown resistor to
ground, which enables the internal reference circuit. Tying
this pin to AVDD powers down the internal reference
generator, allowing the user to provide external voltages
for VREFT (pin 9) and VREFB (pin 8). In addition to the
power consumption reduction (typically 56 mW) which is
now transferred to the external circuitry, it also allows for
a precise setting of the input range. To further remove any
variation with external factors, such as temperature or
supply voltage, the user has direct access to the internal
resistor divider, without any intermediate buffering. The
equivalent circuit for the reference input pins is shown in
Figure 26. The core of the ADC is designed for a 1 V
difference between the reference pins. Nevertheless, the
user can use these pins to set a different input range.
Figure 11 shows the variation on SNR and SFDR for a
sampling rate of 65 MHz and a single-tone input of 80 MHz
at 1 dBFS for different VREFTVREFB voltage settings.
0.1
F
1
F
0.1
F
1
F
VREFT
VREFB
0.1
F
1
F
VBG
0.1
F
Figure 33. Internal Reference Usage
CLOCK INPUTS
The ADS5413 clock input can be driven with either a
differential clock signal or a single ended clock input with
little or no difference in performance between the
single-ended and differential-input configurations (see
internally to AVDD/2 using 5-k
When driven with a single-ended clock input, it is best to
connect the CLKC input to ground with a 0.01-
F capacitor
F to
the clock source.
CLK
ADS5413
CLKC
Square Wave or
Sine Wave
1 Vp-p to 3 Vp-p
0.01
F
0.01
F
Figure 34. AC-Coupled Single-Ended Clock Input
The ADS5413 clock input can also be driven differentially.
In this case, it is best to connect both clock inputs to the
differential input clock signal with 0.01-
F capacitors (see
Figure 35). The differential input swing can vary between
1 V and 6 V with little or no performance degradation (see
CLK
ADS5413
CLKC
Differential Square Wave or
Sine Wave
1 Vp-p to 6 Vp-p
0.01
F
0.01
F
Figure 35. AC-Coupled Differential Clock Input
Although the use of the ac-coupled configuration is
recommended to set up the common mode for the clock,
the ADS5413 can be operated with different common
modes for those cases where the ac configuration can not
be used.
Figure 18 shows the performance of the
ADS5413 versus different clock common modes.