參數(shù)資料
型號: ADS1259BIPWR
廠商: Texas Instruments
文件頁數(shù): 4/48頁
文件大?。?/td> 0K
描述: IC ADC 24BIT SPI 14KSPS 20TSSOP
標準包裝: 2,000
位數(shù): 24
采樣率(每秒): 14k
數(shù)據(jù)接口: 串行,SPI?
轉(zhuǎn)換器數(shù)目: 1
電壓電源: 模擬和數(shù)字,雙 ±
工作溫度: -40°C ~ 125°C
安裝類型: 表面貼裝
封裝/外殼: 20-TSSOP(0.173",4.40mm 寬)
供應商設備封裝: 20-TSSOP
包裝: 帶卷 (TR)
輸入數(shù)目和類型: 2 個單端,單極;2 個單端,雙極;1 個差分,單極;1 個差分,雙極
Programmable
DigitalFilter
2.5V
Reference
DS
Modulator
VREFP
VREFN
AVSS
DGND
AINP
AINN
XTAL2
XTAL1/CLKIN
Control
and
Serial
Interface
Clock
Generator
Out-of-Range
Detection
RESETPWDN
/
DRDY
SCLK
DIN
START
CS
DOUT
Calibration
Engine
f
/8
CLK
SYNCOUT
DVDD
LDO
BYPASS
+1.8V
(DigitalCore)
FLAG
AVDD
REFOUT
ADS1259
SBAS424D
– JUNE 2009 – REVISED AUGUST 2011
OVERVIEW
The
ADS1259
is
a
high-linearity,
low
drift
The digital filter receives the modulator signal and
analog-to-digital converter (ADC) designed for the
provides the digital output. The filter consists of a
needs
of
industrial
process
control,
precision
fifth-order sinc filter followed by a programmable
instrumentation,
and
similar
applications.
The
averager, selectable as either a sinc1 or sinc2. In
converter provides high-resolution, 24-bit output data
sinc1 mode, the filter settles in a single conversion.
at sample rates ranging from 10SPS to 14.4kSPS.
The programmable averaging yields output data rates
from 10SPS to 14.4kSPS.
Figure 32 shows a block diagram of the ADS1259.
The
device
allows
unipolar
or
bipolar
analog
The ADS1259 integrates a low-drift, low-noise +2.5V
power-supply configuration (AVDD
– AVSS = 5V
reference. The internal reference can drive loads up
total). The analog supplies may be set to single +5V
to
±10mA. The ADS1259 also operates from an
to accept unipolar (or offset-bipolar) signals or the
external reference if desired. The reference input is
supplies can be set to
±2.5V to accept true bipolar
buffered to reduce loading of external circuits.
signals. The operating range of the digital power
An onboard oscillator is provided as the clock source
supply (DVDD) is 2.7V to 5V.
for the device. Optionally, an external crystal can be
An internal low dropout regulator (LDO) powers the
used. As a third clock option, the device can be
digital core from the DVDD supply while the device
driven by an external clock source. SYNCOUT is an
I/O operates directly from DVDD. BYPASS is the
output that provides a 1/8 rate clock intended to drive
LDO output and requires a 0.1
μF or larger capacitor
the chopping clock input of the PGA280.
to ground.
Gain and offset registers scale the digital filter output
The inherently stable, fourth-order,
ΔΣ modulator
to produce the final code value. On-command
measures the differential input signal [VIN = (AINP –
calibration corrects for system offset and gain errors.
AINN)] against the differential reference [VREF =
An SPI-compatible serial interface provides the
(VREFP
– VREFN)]. A fast responding out-of-range
control and configuration as well as the data interface
detector flags the output data if the input should
to the ADS1259. Onboard registers combined with
over-range while converting.
commands are used to control and configure the
device.
The RESET/PWDN pin is dual function. A momentary
low resets the device and, if the pin is held low,
powers down the device. The START pin, as well as
commands, controls the conversions.
Figure 32. ADS1259 Block Diagram
12
Copyright
2009–2011, Texas Instruments Incorporated
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