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參數(shù)資料
| 型號： | ADS1259BIPWR |
| 廠商： | Texas Instruments |
| 文件頁數(shù)： | 17/48頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC ADC 24BIT SPI 14KSPS 20TSSOP |
| 標(biāo)準(zhǔn)包裝： | 2,000 |
| 位數(shù)： | 24 |
| 采樣率（每秒）： | 14k |
| 數(shù)據(jù)接口： | 串行，SPI? |
| 轉(zhuǎn)換器數(shù)目： | 1 |
| 電壓電源： | 模擬和數(shù)字，雙 ± |
| 工作溫度： | -40°C ~ 125°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 20-TSSOP（0.173"，4.40mm 寬） |
| 供應(yīng)商設(shè)備封裝： | 20-TSSOP |
| 包裝： | 帶卷 (TR) |
| 輸入數(shù)目和類型： | 2 個(gè)單端，單極；2 個(gè)單端，雙極；1 個(gè)差分，單極；1 個(gè)差分，雙極 |
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STARTPin
DRDY
Halted
Single
Conversion
Halted
Single
Conversion
OR
START
DRDY
DOUT
Settled
Data
START
Pin
START
Command
or
t
SET
(1)
7thFallingSCLKEdgeofOpcode
V
=AINP
AINN
-
IN
SettledV
IN
SBAS424D
– JUNE 2009 – REVISED AUGUST 2011
Pulse Control Mode (PULSE Bit = 1)
Settling Time Using START
In the Pulse Control mode, the ADS1259 performs a
When START goes high (via pin or command) a
single conversion when either the START pin is taken
delay may be programmed before the conversion
high or when the START command is sent. As seen
filter cycle begins. The programmable delay may be
in Figure 52, DRDY goes high when the conversion is
useful to provide time for external circuits (such as
started. When the conversion is complete, DRDY
after an external signal mux change), before the
goes low and further conversions are halted. To start
reading is started. Register bits DELAY[2:0] set the
a new conversion, transition the START pin back to
initial delay time as shown in Table 8.
high, or transmit the START opcode again.
Table 8. Initial START Delay
DELAY[2:0]
tDELAY (tCLK)
000
0
001
64
8.68
010
128
17.4
011
256
34.7
100
512
69.4
101
1024
139
110
2048
278
111
4096
556
(1) START opcode command takes effect on the seventh SCLK
falling edge.
(1) fCLK = 7.3728MHz.
Figure 52. Pulse Control Mode
After the programmable delay, the digital filter is reset
and a new conversion is started. DRDY goes low
when data are ready. There is no need to ignore or
CONVERSION SETTLING TIME
discard data; the data are completely settled. The
total time to perform the first conversion is the sum of
The ADS1259 features a digital filter architecture in
the programmable delay time and the settling of the
which settling time can be traded for wide filter
notches, resulting in improved line-cycle rejection.
This trade-off is determined by the selection of the
shows the settling time with programmable delay
sinc1 or sinc2 filter. The sinc1 filter settles in a single
equal to '0'.
cycle while the sinc2 filter provides wide-width filter
notches. The settling time of the ADS1259 is different
Table 9. Settling Time Using START
if START is used to begin conversions or if the
ADS1259 is free-running the conversions. These
DATA RATE
modes are explained in the Settling Time Using
(SPS)
sinc1
sinc2
and
10
100
200
Converting sections.
16.6
60.3
120
50
20.3
40.4
60
17.0
33.7
400
2.85
5.42
1200
1.18
2.10
3600
0.632
0.980
14,400
0.424
0.563
(1) fCLK = 7.3728MHz, DELAY[2:0] = 000.
(1) tSET = initial start delay plus the new conversion cycle time.
Figure 53. Data Retrieval Time After START
24
Copyright
2009–2011, Texas Instruments Incorporated
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| ADS1259EVM-PDK | 功能描述:數(shù)據(jù)轉(zhuǎn)換 IC 開發(fā)工具 ADS1259 Perf Demo Kit RoHS:否 制造商:Texas Instruments 產(chǎn)品:Demonstration Kits 類型:ADC 工具用于評估:ADS130E08 接口類型:SPI 工作電源電壓:- 6 V to + 6 V |
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