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參數(shù)資料
| 型號： | ADS1252U |
| 廠商： | Texas Instruments |
| 文件頁數(shù)： | 6/21頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC ADC 24-BIT SER 41.7KHZ 8-SOIC |
| 產(chǎn)品培訓(xùn)模塊： | Data Converter Basics |
| 視頻文件： | Nuts and Bolts of the Delta-Sigma Converter |
| 標(biāo)準(zhǔn)包裝： | 75 |
| 位數(shù)： | 24 |
| 采樣率（每秒）： | 41.7k |
| 數(shù)據(jù)接口： | 串行 |
| 轉(zhuǎn)換器數(shù)目： | 1 |
| 功率耗散（最大）： | 40mW |
| 電壓電源： | 單電源 |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 8-SOIC（0.154"，3.90mm 寬） |
| 供應(yīng)商設(shè)備封裝： | 8-SOIC |
| 包裝： | 管件 |
| 輸入數(shù)目和類型： | 1 個差分，雙極 |
| 產(chǎn)品目錄頁面： | 889 (CN2011-ZH PDF) |
| 配用： | 296-19906-ND - EVAL MOD FOR ADS1252 |
ADS1252
14
SBAS127D
www.ti.com
ISOLATION
The serial interface of the ADS1252 provides for simple
isolation methods. The CLK signal can be local to the
ADS1252, which then only requires two signals (SCLK and
DOUT/DRDY) to be used for isolated data acquisition.
LAYOUT
POWER SUPPLY
The power supply should be well regulated and low noise.
For designs requiring very high resolution from the ADS1252,
power-supply rejection will be a concern. Avoid running
digital lines under the device because they can couple noise
onto the die. High-frequency noise can capacitively couple
into the analog portion of the device and will alias back into
the passband of the digital filter, affecting the conversion
result.
GROUNDING
The analog and digital sections of the system design must be
carefully and cleanly partitionedl; each section must have its
own ground plane with no overlap between them. GND must
be connected to the analog ground plane, as well as all other
analog grounds. Do not join the analog and digital ground
planes on the board, but instead connect the two with a
moderate signal trace. For multiple converters, connect the
two ground planes at one location as central to all of the
converters as possible. In some cases, experimentation is
required to find the best point to connect the two planes
together. The printed circuit board can be designed to pro-
vide different analog/digital ground connections via short
jumpers; the initial prototype can be used to establish which
connection works best.
DECOUPLING
Good decoupling practices must be used for the ADS1252
and for all components in the design. All decoupling capaci-
tors, and specifically the 0.1
F ceramic capacitors, must be
placed as close as possible to the pin being decoupled. A
1
F to 10F capacitor, in parallel with a 0.1F ceramic
capacitor, must be used to decouple VDD to GND.
SYSTEM CONSIDERATIONS
The recommendations for power supplies and grounding
change depending on the requirements and specific design
of the overall system. Achieving 24 bits of noise performance
is a great deal more difficult than achieving 12 bits of noise
performance. In general, a system can be broken up into four
different stages:
Analog Processing
Analog Portion of the ADS1252
Digital Portion of the ADS1252
Digital Processing
For the simplest system consisting of minimal analog signal
processing (basic filtering and gain), a microcontroller, and
one clock source, one can achieve high resolution by power-
ing all components by a common power supply. In addition,
all components can share a common ground plane; thus,
there would be no distinctions between analog power and
ground, and digital power and ground. The layout must still
include a power plane, a ground plane, and careful decoupling.
In a more extreme case, the design can include:
Multiple ADS1252s
Extensive Analog Signal Processing
One or More Microcontrollers, Digital Signal Processors, or
Microprocessors
Many Different Clock Sources
Interconnections to Various Other Systems
High resolution will be very difficult to achieve for this design.
The approach would be to break the system into as many
different parts as possible. For example, each ADS1252 may
have its own analog processing front end.
DEFINITION OF TERMS
An attempt has been made to be consistent with the termi-
nology used in this data sheet. In that regard, the definition
of each term is given as follows:
Analog-Input Differential Voltage—for an analog signal
that is fully differential, the voltage range can be compared to
that of an instrumentation amplifier. For example, if both
analog inputs of the ADS1252 are at 2.048V, the differential
voltage is 0V; however, if one analog input is at 0V and the
other analog input is at 4.096V, then the differential voltage
magnitude is 4.096V. This is the case regardless of which
input is at 0V and which is at 4.096V. The digital-output
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| ADS1252U | 制造商:Texas Instruments 功能描述:IC 24BIT ADC 41.7KSPS SMD |
| ADS1252U/2K5 | 功能描述:模數(shù)轉(zhuǎn)換器 - ADC ResolutionPlus 24-Bit 40kHz RoHS:否 制造商:Texas Instruments 通道數(shù)量:2 結(jié)構(gòu):Sigma-Delta 轉(zhuǎn)換速率:125 SPs to 8 KSPs 分辨率:24 bit 輸入類型:Differential 信噪比:107 dB 接口類型:SPI 工作電源電壓:1.7 V to 3.6 V, 2.7 V to 5.25 V 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:VQFN-32 |
| ADS1252U/2K5G4 | 功能描述:模數(shù)轉(zhuǎn)換器 - ADC ResolutionPlus 24-Bit 40kHz RoHS:否 制造商:Texas Instruments 通道數(shù)量:2 結(jié)構(gòu):Sigma-Delta 轉(zhuǎn)換速率:125 SPs to 8 KSPs 分辨率:24 bit 輸入類型:Differential 信噪比:107 dB 接口類型:SPI 工作電源電壓:1.7 V to 3.6 V, 2.7 V to 5.25 V 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:VQFN-32 |
| ADS1252UG4 | 功能描述:模數(shù)轉(zhuǎn)換器 - ADC ResolutionPlus 24-Bit 40kHz RoHS:否 制造商:Texas Instruments 通道數(shù)量:2 結(jié)構(gòu):Sigma-Delta 轉(zhuǎn)換速率:125 SPs to 8 KSPs 分辨率:24 bit 輸入類型:Differential 信噪比:107 dB 接口類型:SPI 工作電源電壓:1.7 V to 3.6 V, 2.7 V to 5.25 V 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:VQFN-32 |
| ADS1253 | 制造商:TI 制造商全稱:Texas Instruments 功能描述:24-Bit, 20kHz, Low Power ANALOG-TO-DIGITAL CONVERTER |
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