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參數(shù)資料
| 型號： | ADS1252U |
| 廠商： | Texas Instruments |
| 文件頁數(shù)： | 21/21頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC ADC 24-BIT SER 41.7KHZ 8-SOIC |
| 產品培訓模塊： | Data Converter Basics |
| 視頻文件： | Nuts and Bolts of the Delta-Sigma Converter |
| 標準包裝： | 75 |
| 位數(shù)： | 24 |
| 采樣率（每秒）： | 41.7k |
| 數(shù)據(jù)接口： | 串行 |
| 轉換器數(shù)目： | 1 |
| 功率耗散（最大）： | 40mW |
| 電壓電源： | 單電源 |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 8-SOIC（0.154"，3.90mm 寬） |
| 供應商設備封裝： | 8-SOIC |
| 包裝： | 管件 |
| 輸入數(shù)目和類型： | 1 個差分，雙極 |
| 產品目錄頁面： | 889 (CN2011-ZH PDF) |
| 配用： | 296-19906-ND - EVAL MOD FOR ADS1252 |
ADS1252
9
SBAS127D
www.ti.com
The digital filter requires five conversions to fully settle. The
modulator has an oversampling ratio of 64; therefore, it
requires 5 64, or 320 modulator results, or clocks, to fully
settle. As the modulator clock is derived from the system
clock (CLK) (modulator clock = CLK
÷ 6), the number of
system clocks required for the digital filter to fully settle is
5 64 6, or 1920 CLKs. This means that any significant step
change at the analog input requires five full conversions to
settle. However, if the analog input change occurs asynchro-
nously to the DOUT/DRDY pulse, then six conversions are
required to ensure full settling.
CONTROL LOGIC
The control logic is used for communications and control of
the ADS1252.
Power-Up Sequence
Prior to power-up, all digital and analog-input pins must be
LOW. At the time of power-up, these signal inputs can be
biased to a voltage other than 0V, however, they must never
exceed +VDD.
Once the ADS1252 powers up, the DOUT/DRDY line pulses
LOW on the first conversion; this data is not valid. The sixth
pulse of DOUT/DRDY is valid data from the analog input
signal.
DOUT/DRDY
The DOUT/DRDY output signal alternates between two
modes of operation. The first mode of operation is the Data
Ready (DRDY) mode to indicate that new data has been
loaded into the data-output register and is ready to be read.
The second mode of operation is the Data Output (DOUT)
mode and is used to serially shift data out of the Data Output
Register (DOR). See Figure 11 for the time domain partition-
ing of the DRDY and DOUT function.
See Figure 12 for the basic timing of DOUT/DRDY. During
the time defined by t2, t3, and t4, the DOUT/DRDY
pin functions in DRDY mode. The state of the
DOUT/DRDY pin is HIGH prior to the internal transfer of new
data to the DOR. The result of the A/D conversion is written
For example, if the rejection of power-line frequencies is
desired, then the data-output rate can simply be set to the
power-line frequency. For 50Hz rejection, the system CLK
frequency must be 19.200kHz, and this will set the data-
output rate to 50Hz (see Table I and Figure 4). For 60Hz
rejection, the system CLK frequency must be 20.040kHz,
and this will set the data-output rate to 60Hz (see Table I and
Figure 5). If both 50Hz and 60Hz rejection is required, then
the system CLK must be 3.840kHz; this will set the data-
output rate to 10Hz and reject both 50Hz and 60Hz (see Table
I and Figure 6).
There is an additional benefit in using a lower data-output
rate: it provides better rejection of signals in the frequency
band of interest. For example, with a 50Hz data-output rate,
a significant signal at 75Hz can alias back into the passband
at 25Hz; this is due to the fact that rejection at 75Hz must
only be 66dB in the stopband—frequencies higher than the
first-notch frequency (see Figure 4). However, setting the
data-output rate to 10Hz will provide 135dB rejection at 75Hz
(see Figure 6). A similar benefit is gained at frequencies near
the data-output rate (see Figures 7, 8, 9, and 10). For
example, with a 50Hz data-output rate, rejection at 55Hz may
only be 105dB (see Figure 7); however, with a 10Hz data-
output rate, rejection at 55Hz will be 122dB (see Figure 8).
If a slower data-output rate does not meet the system
requirements, then the analog front end can be designed to
provide the needed attenuation to prevent aliasing. Addition-
ally, the data-output rate can be increased and additional
digital filtering can be done in the processor or controller.
Application note SBAA103,
A Spreadsheet to Calculate the
Frequency Response of the ADS1250-54 (available for down-
load at www.ti.com) provides a simple tool for calculating the
ADS1250 frequency response for any CLK frequency.
The digital filter is described by the following transfer func-
tion:
Hf
f
or
Hz
z
MOD
()
sin
sin
()
–
=
=
(
)
π
64
1
64
1
5
64
1
5
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相關代理商/技術參數(shù) |
參數(shù)描述 |
|---|---|
| ADS1252U | 制造商:Texas Instruments 功能描述:IC 24BIT ADC 41.7KSPS SMD |
| ADS1252U/2K5 | 功能描述:模數(shù)轉換器 - ADC ResolutionPlus 24-Bit 40kHz RoHS:否 制造商:Texas Instruments 通道數(shù)量:2 結構:Sigma-Delta 轉換速率:125 SPs to 8 KSPs 分辨率:24 bit 輸入類型:Differential 信噪比:107 dB 接口類型:SPI 工作電源電壓:1.7 V to 3.6 V, 2.7 V to 5.25 V 最大工作溫度:+ 85 C 安裝風格:SMD/SMT 封裝 / 箱體:VQFN-32 |
| ADS1252U/2K5G4 | 功能描述:模數(shù)轉換器 - ADC ResolutionPlus 24-Bit 40kHz RoHS:否 制造商:Texas Instruments 通道數(shù)量:2 結構:Sigma-Delta 轉換速率:125 SPs to 8 KSPs 分辨率:24 bit 輸入類型:Differential 信噪比:107 dB 接口類型:SPI 工作電源電壓:1.7 V to 3.6 V, 2.7 V to 5.25 V 最大工作溫度:+ 85 C 安裝風格:SMD/SMT 封裝 / 箱體:VQFN-32 |
| ADS1252UG4 | 功能描述:模數(shù)轉換器 - ADC ResolutionPlus 24-Bit 40kHz RoHS:否 制造商:Texas Instruments 通道數(shù)量:2 結構:Sigma-Delta 轉換速率:125 SPs to 8 KSPs 分辨率:24 bit 輸入類型:Differential 信噪比:107 dB 接口類型:SPI 工作電源電壓:1.7 V to 3.6 V, 2.7 V to 5.25 V 最大工作溫度:+ 85 C 安裝風格:SMD/SMT 封裝 / 箱體:VQFN-32 |
| ADS1253 | 制造商:TI 制造商全稱:Texas Instruments 功能描述:24-Bit, 20kHz, Low Power ANALOG-TO-DIGITAL CONVERTER |
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